radeonsi: move texture storage allocation outside of radeonsi
possible code sharing with radv Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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58ccadfc5c
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e4c84d8678
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@ -1679,7 +1679,61 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
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return r;
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return r;
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if (info->chip_class >= GFX9)
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if (info->chip_class >= GFX9)
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return gfx9_compute_surface(addrlib, info, config, mode, surf);
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r = gfx9_compute_surface(addrlib, info, config, mode, surf);
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else
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else
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return gfx6_compute_surface(addrlib, info, config, mode, surf);
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r = gfx6_compute_surface(addrlib, info, config, mode, surf);
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if (r)
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return r;
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/* Determine the memory layout of multiple allocations in one buffer. */
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surf->total_size = surf->surf_size;
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if (surf->htile_size) {
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surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
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surf->total_size = surf->htile_offset + surf->htile_size;
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}
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if (surf->fmask_size) {
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assert(config->info.samples >= 2);
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surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
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surf->total_size = surf->fmask_offset + surf->fmask_size;
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}
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/* Single-sample CMASK is in a separate buffer. */
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if (surf->cmask_size && config->info.samples >= 2) {
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surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
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surf->total_size = surf->cmask_offset + surf->cmask_size;
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}
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if (surf->dcc_size &&
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(info->use_display_dcc_unaligned ||
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info->use_display_dcc_with_retile_blit ||
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!(surf->flags & RADEON_SURF_SCANOUT))) {
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surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
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surf->total_size = surf->dcc_offset + surf->dcc_size;
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if (info->chip_class >= GFX9 &&
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surf->u.gfx9.dcc_retile_num_elements) {
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/* Add space for the displayable DCC buffer. */
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surf->display_dcc_offset =
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align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
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surf->total_size = surf->display_dcc_offset +
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surf->u.gfx9.display_dcc_size;
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/* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
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surf->dcc_retile_map_offset =
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align64(surf->total_size, info->tcc_cache_line_size);
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if (surf->u.gfx9.dcc_retile_use_uint16) {
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surf->total_size = surf->dcc_retile_map_offset +
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surf->u.gfx9.dcc_retile_num_elements * 2;
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} else {
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surf->total_size = surf->dcc_retile_map_offset +
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surf->u.gfx9.dcc_retile_num_elements * 4;
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}
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}
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}
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return 0;
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}
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}
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@ -227,6 +227,15 @@ struct radeon_surf {
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uint32_t cmask_slice_size;
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uint32_t cmask_slice_size;
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uint32_t cmask_alignment;
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uint32_t cmask_alignment;
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/* All buffers combined. */
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uint64_t htile_offset;
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uint64_t fmask_offset;
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uint64_t cmask_offset;
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uint64_t dcc_offset;
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uint64_t display_dcc_offset;
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uint64_t dcc_retile_map_offset;
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uint64_t total_size;
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union {
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union {
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/* Return values for GFX8 and older.
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/* Return values for GFX8 and older.
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*
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*
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@ -1243,10 +1243,7 @@ si_texture_create_object(struct pipe_screen *screen,
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/* don't include stencil-only formats which we don't support for rendering */
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/* don't include stencil-only formats which we don't support for rendering */
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tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
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tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
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tex->surface = *surface;
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tex->surface = *surface;
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tex->size = tex->surface.surf_size;
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tex->tc_compatible_htile = tex->surface.htile_size != 0 &&
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tex->tc_compatible_htile = tex->surface.htile_size != 0 &&
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(tex->surface.flags &
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(tex->surface.flags &
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RADEON_SURF_TC_COMPATIBLE_HTILE);
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RADEON_SURF_TC_COMPATIBLE_HTILE);
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@ -1276,6 +1273,15 @@ si_texture_create_object(struct pipe_screen *screen,
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*/
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*/
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tex->ps_draw_ratio = 0;
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tex->ps_draw_ratio = 0;
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/* TODO: remove these */
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tex->fmask_offset = tex->surface.fmask_offset;
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tex->cmask_offset = tex->surface.cmask_offset;
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tex->htile_offset = tex->surface.htile_offset;
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tex->dcc_offset = tex->surface.dcc_offset;
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tex->display_dcc_offset = tex->surface.display_dcc_offset;
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tex->dcc_retile_map_offset = tex->surface.dcc_retile_map_offset;
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tex->size = tex->surface.total_size;
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if (tex->is_depth) {
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if (tex->is_depth) {
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if (sscreen->info.chip_class >= GFX9) {
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if (sscreen->info.chip_class >= GFX9) {
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tex->can_sample_z = true;
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tex->can_sample_z = true;
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@ -1294,55 +1300,11 @@ si_texture_create_object(struct pipe_screen *screen,
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}
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}
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tex->db_compatible = surface->flags & RADEON_SURF_ZBUFFER;
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tex->db_compatible = surface->flags & RADEON_SURF_ZBUFFER;
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if (tex->surface.htile_size) {
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tex->htile_offset = align64(tex->size,
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tex->surface.htile_alignment);
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tex->size = tex->htile_offset + tex->surface.htile_size;
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}
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} else {
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} else {
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if (tex->surface.fmask_size) {
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if (tex->surface.cmask_offset) {
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/* Allocate FMASK. */
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tex->fmask_offset = align64(tex->size,
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tex->surface.fmask_alignment);
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tex->size = tex->fmask_offset + tex->surface.fmask_size;
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/* Allocate CMASK. */
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tex->cmask_offset = align64(tex->size, tex->surface.cmask_alignment);
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tex->size = tex->cmask_offset + tex->surface.cmask_size;
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tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
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tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
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tex->cmask_buffer = &tex->buffer;
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tex->cmask_buffer = &tex->buffer;
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}
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}
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if (tex->surface.dcc_size &&
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(sscreen->info.use_display_dcc_unaligned ||
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sscreen->info.use_display_dcc_with_retile_blit ||
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!(tex->surface.flags & RADEON_SURF_SCANOUT))) {
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/* Add space for the DCC buffer. */
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tex->dcc_offset = align64(tex->size, tex->surface.dcc_alignment);
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tex->size = tex->dcc_offset + tex->surface.dcc_size;
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if (sscreen->info.chip_class >= GFX9 &&
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tex->surface.u.gfx9.dcc_retile_num_elements) {
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/* Add space for the displayable DCC buffer. */
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tex->display_dcc_offset =
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align64(tex->size, tex->surface.u.gfx9.display_dcc_alignment);
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tex->size = tex->display_dcc_offset +
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tex->surface.u.gfx9.display_dcc_size;
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/* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
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tex->dcc_retile_map_offset =
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align64(tex->size, sscreen->info.tcc_cache_line_size);
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if (tex->surface.u.gfx9.dcc_retile_use_uint16) {
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tex->size = tex->dcc_retile_map_offset +
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tex->surface.u.gfx9.dcc_retile_num_elements * 2;
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} else {
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tex->size = tex->dcc_retile_map_offset +
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tex->surface.u.gfx9.dcc_retile_num_elements * 4;
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}
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}
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}
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}
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}
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/* Now create the backing buffer. */
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/* Now create the backing buffer. */
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@ -432,9 +432,30 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
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si_compute_cmask(&ws->info, &config, surf_ws);
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si_compute_cmask(&ws->info, &config, surf_ws);
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}
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}
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if (ws->gen == DRV_SI)
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if (ws->gen == DRV_SI) {
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si_compute_htile(&ws->info, surf_ws, util_num_layers(tex, 0));
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si_compute_htile(&ws->info, surf_ws, util_num_layers(tex, 0));
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/* Determine the memory layout of multiple allocations in one buffer. */
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surf_ws->total_size = surf_ws->surf_size;
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if (surf_ws->htile_size) {
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surf_ws->htile_offset = align64(surf_ws->total_size, surf_ws->htile_alignment);
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surf_ws->total_size = surf_ws->htile_offset + surf_ws->htile_size;
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}
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if (surf_ws->fmask_size) {
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assert(tex->nr_samples >= 2);
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surf_ws->fmask_offset = align64(surf_ws->total_size, surf_ws->fmask_alignment);
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surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size;
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}
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/* Single-sample CMASK is in a separate buffer. */
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if (surf_ws->cmask_size && tex->nr_samples >= 2) {
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surf_ws->cmask_offset = align64(surf_ws->total_size, surf_ws->cmask_alignment);
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surf_ws->total_size = surf_ws->cmask_offset + surf_ws->cmask_size;
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}
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}
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return 0;
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return 0;
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}
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}
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