nvc0/ir: add support for reading outputs in tess control shaders
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
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@ -1203,6 +1203,16 @@ bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
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if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
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info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
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0x1 : 0x2;
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} else
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if (src.getFile() == TGSI_FILE_OUTPUT) {
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if (src.isIndirect(0)) {
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// We don't know which one is accessed, just mark everything for
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// reading. This is an extremely unlikely occurrence.
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for (unsigned i = 0; i < info->numOutputs; ++i)
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info->out[i].oread = 1;
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} else {
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info->out[src.getIndex(0)].oread = 1;
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}
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}
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if (src.getFile() != TGSI_FILE_INPUT)
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continue;
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@ -1521,6 +1531,7 @@ Converter::fetchSrc(int s, int c)
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if (src.is2D()) {
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switch (src.getFile()) {
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case TGSI_FILE_OUTPUT:
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case TGSI_FILE_INPUT:
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dimRel = getVertexBase(s);
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break;
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@ -1607,8 +1618,10 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
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ld->perPatch = info->in[idx].patch;
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return ld->getDef(0);
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case TGSI_FILE_OUTPUT:
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assert(!"load from output file");
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return NULL;
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assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
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ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
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ld->perPatch = info->out[idx].patch;
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return ld->getDef(0);
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case TGSI_FILE_SYSTEM_VALUE:
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assert(!ptr);
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return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
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@ -1815,6 +1815,9 @@ NVC0LoweringPass::visit(Instruction *i)
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i->setIndirect(0, 0, ptr);
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i->subOp = NV50_IR_SUBOP_LDC_IS;
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}
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} else if (i->src(0).getFile() == FILE_SHADER_OUTPUT) {
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assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
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i->op = OP_VFETCH;
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}
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break;
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case OP_ATOM:
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