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ilo: use genhw command opcodes 

Replace ILO_GPE_MI and ILO_GPE_CMD with magic values by descriptive genhw
macros.
This commit is contained in:
Chia-I Wu 2014-08-21 12:51:08 +08:00
parent 6c73478223
commit e3c251071b
5 changed files with 182 additions and 132 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/gallium/drivers/ilo/genhw/genhw.h
View File

@ -37,15 +37,21 @@
#include "gen_eu_isa.xml.h"
#include "gen_eu_message.xml.h"
#define GEN_MI_CMD(op) (GEN6_MI_TYPE_MI | GEN6_MI_OPCODE_ ## op)
#define GEN_MI_CMD(gen, op) (GEN6_MI_TYPE_MI | gen ## _MI_OPCODE_ ## op)
#define GEN6_MI_CMD(op) GEN_MI_CMD(GEN6, op)
#define GEN7_MI_CMD(op) GEN_MI_CMD(GEN7, op)
#define GEN_BLITTER_CMD(op) \
(GEN6_BLITTER_TYPE_BLITTER | GEN6_BLITTER_OPCODE_ ## op)
#define GEN_BLITTER_CMD(gen, op) \
(GEN6_BLITTER_TYPE_BLITTER | gen ## _BLITTER_OPCODE_ ## op)
#define GEN6_BLITTER_CMD(op) GEN_BLITTER_CMD(GEN6, op)
#define GEN_RENDER_CMD(subtype, op) \
(GEN6_RENDER_TYPE_RENDER | \
GEN6_RENDER_SUBTYPE_ ## subtype | \
GEN6_RENDER_OPCODE_ ## op)
#define GEN_RENDER_CMD(subtype, gen, op) \
(GEN6_RENDER_TYPE_RENDER | \
GEN6_RENDER_SUBTYPE_ ## subtype | \
gen ## _RENDER_OPCODE_ ## op)
#define GEN6_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN6, op)
#define GEN7_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN7, op)
#define GEN75_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN75, op)
static inline bool
gen_is_snb(int devid)

21
src/gallium/drivers/ilo/ilo_blitter_blt.c
View File

@ -35,13 +35,6 @@
#include "ilo_resource.h"
#include "ilo_blitter.h"
#define MI_FLUSH_DW GEN_MI_CMD(MI_FLUSH_DW)
#define MI_LOAD_REGISTER_IMM GEN_MI_CMD(MI_LOAD_REGISTER_IMM)
#define COLOR_BLT GEN_BLITTER_CMD(COLOR_BLT)
#define XY_COLOR_BLT GEN_BLITTER_CMD(XY_COLOR_BLT)
#define SRC_COPY_BLT GEN_BLITTER_CMD(SRC_COPY_BLT)
#define XY_SRC_COPY_BLT GEN_BLITTER_CMD(XY_SRC_COPY_BLT)
enum gen6_blt_mask {
GEN6_BLT_MASK_8,
GEN6_BLT_MASK_16,
@ -67,9 +60,10 @@ static void
gen6_emit_MI_FLUSH_DW(struct ilo_dev_info *dev, struct ilo_cp *cp)
{
const uint8_t cmd_len = 4;
const uint32_t dw0 = GEN6_MI_CMD(MI_FLUSH_DW) | (cmd_len - 2);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, MI_FLUSH_DW | (cmd_len - 2));
ilo_cp_write(cp, dw0);
ilo_cp_write(cp, 0);
ilo_cp_write(cp, 0);
ilo_cp_write(cp, 0);
@ -82,9 +76,10 @@ gen6_emit_MI_LOAD_REGISTER_IMM(struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint8_t cmd_len = 3;
const uint32_t dw0 = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM) | (cmd_len - 2);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, MI_LOAD_REGISTER_IMM | (cmd_len - 2));
ilo_cp_write(cp, dw0);
ilo_cp_write(cp, reg);
ilo_cp_write(cp, val);
ilo_cp_end(cp);
@ -136,7 +131,7 @@ gen6_emit_COLOR_BLT(struct ilo_dev_info *dev,
const int cpp = gen6_translate_blt_cpp(value_mask);
uint32_t dw0, dw1;
dw0 = COLOR_BLT |
dw0 = GEN6_BLITTER_CMD(COLOR_BLT) |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);
@ -174,7 +169,7 @@ gen6_emit_XY_COLOR_BLT(struct ilo_dev_info *dev,
int dst_align, dst_pitch_shift;
uint32_t dw0, dw1;
dw0 = XY_COLOR_BLT |
dw0 = GEN6_BLITTER_CMD(XY_COLOR_BLT) |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);
@ -224,7 +219,7 @@ gen6_emit_SRC_COPY_BLT(struct ilo_dev_info *dev,
const int cpp = gen6_translate_blt_cpp(value_mask);
uint32_t dw0, dw1;
dw0 = SRC_COPY_BLT |
dw0 = GEN6_BLITTER_CMD(SRC_COPY_BLT) |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);
@ -271,7 +266,7 @@ gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev,
int src_align, src_pitch_shift;
uint32_t dw0, dw1;
dw0 = XY_SRC_COPY_BLT |
dw0 = GEN6_BLITTER_CMD(XY_SRC_COPY_BLT) |
gen6_translate_blt_write_mask(write_mask) |
(cmd_len - 2);

7
src/gallium/drivers/ilo/ilo_cp.c
View File

@ -30,9 +30,6 @@
#include "ilo_cp.h"
#define MI_NOOP GEN_MI_CMD(MI_NOOP)
#define MI_BATCH_BUFFER_END GEN_MI_CMD(MI_BATCH_BUFFER_END)
/* the size of the private space */
static const int ilo_cp_private = 2;
@ -114,7 +111,7 @@ ilo_cp_end_buffer(struct ilo_cp *cp)
assert(cp->used + 2 <= cp->size);
cp->ptr[cp->used++] = MI_BATCH_BUFFER_END;
cp->ptr[cp->used++] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 107:
@ -123,7 +120,7 @@ ilo_cp_end_buffer(struct ilo_cp *cp)
* length."
*/
if (cp->used & 1)
cp->ptr[cp->used++] = MI_NOOP;
cp->ptr[cp->used++] = GEN6_MI_CMD(MI_NOOP);
}
/**

99
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View File

@ -41,11 +41,6 @@
#define ILO_GPE_VALID_GEN(dev, min_gen, max_gen) \
assert((dev)->gen >= ILO_GEN(min_gen) && (dev)->gen <= ILO_GEN(max_gen))
#define ILO_GPE_MI(op) (0x0 << 29 | (op) << 23)
#define ILO_GPE_CMD(pipeline, op, subop) \
(0x3 << 29 | (pipeline) << 27 | (op) << 24 | (subop) << 16)
/**
* Translate winsys tiling to hardware tiling.
*/
@ -249,7 +244,7 @@ gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
uint64_t val, bool store_qword,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x20);
const uint32_t cmd = GEN6_MI_CMD(MI_STORE_DATA_IMM);
const uint8_t cmd_len = (store_qword) ? 5 : 4;
/* must use GGTT on GEN6 as in PIPE_CONTROL */
const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
@ -277,7 +272,7 @@ gen6_emit_MI_LOAD_REGISTER_IMM(const struct ilo_dev_info *dev,
uint32_t reg, uint32_t val,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x22);
const uint32_t cmd = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -296,7 +291,7 @@ gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
struct intel_bo *bo, uint32_t bo_offset,
uint32_t reg, struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x24);
const uint32_t cmd = GEN6_MI_CMD(MI_STORE_REGISTER_MEM);
const uint8_t cmd_len = 3;
/* must use GGTT on GEN6 as in PIPE_CONTROL */
const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
@ -317,7 +312,7 @@ gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
struct intel_bo *bo, uint32_t bo_offset,
uint32_t report_id, struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_MI(0x28);
const uint32_t cmd = GEN6_MI_CMD(MI_REPORT_PERF_COUNT);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -348,7 +343,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
uint32_t instruction_size,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x0, 0x1, 0x01);
const uint32_t cmd = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS);
const uint8_t cmd_len = 10;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -406,7 +401,7 @@ gen6_emit_STATE_SIP(const struct ilo_dev_info *dev,
uint32_t sip,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x0, 0x1, 0x02);
const uint32_t cmd = GEN6_RENDER_CMD(COMMON, STATE_SIP);
const uint8_t cmd_len = 2;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -422,7 +417,7 @@ gen6_emit_3DSTATE_VF_STATISTICS(const struct ilo_dev_info *dev,
bool enable,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x1, 0x0, 0x0b);
const uint32_t cmd = GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS);
const uint8_t cmd_len = 1;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -437,7 +432,7 @@ gen6_emit_PIPELINE_SELECT(const struct ilo_dev_info *dev,
int pipeline,
struct ilo_cp *cp)
{
const int cmd = ILO_GPE_CMD(0x1, 0x1, 0x04);
const int cmd = GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT);
const uint8_t cmd_len = 1;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -456,7 +451,7 @@ gen6_emit_MEDIA_VFE_STATE(const struct ilo_dev_info *dev,
int urb_entry_size,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x2, 0x0, 0x00);
const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_VFE_STATE);
const uint8_t cmd_len = 8;
uint32_t dw2, dw4;
@ -487,7 +482,7 @@ gen6_emit_MEDIA_CURBE_LOAD(const struct ilo_dev_info *dev,
uint32_t buf, int size,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x2, 0x0, 0x01);
const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_CURBE_LOAD);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(dev, 6, 6);
@ -509,7 +504,8 @@ gen6_emit_MEDIA_INTERFACE_DESCRIPTOR_LOAD(const struct ilo_dev_info *dev,
uint32_t offset, int num_ids,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x2, 0x0, 0x02);
const uint32_t cmd =
GEN6_RENDER_CMD(MEDIA, MEDIA_INTERFACE_DESCRIPTOR_LOAD);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(dev, 6, 6);
@ -530,7 +526,7 @@ gen6_emit_MEDIA_GATEWAY_STATE(const struct ilo_dev_info *dev,
int id, int byte, int thread_count,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x2, 0x0, 0x03);
const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_GATEWAY_STATE);
const uint8_t cmd_len = 2;
uint32_t dw1;
@ -552,7 +548,7 @@ gen6_emit_MEDIA_STATE_FLUSH(const struct ilo_dev_info *dev,
int barrier_mask,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x2, 0x0, 0x04);
const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_STATE_FLUSH);
const uint8_t cmd_len = 2;
uint32_t dw1;
@ -581,7 +577,7 @@ gen6_emit_3DSTATE_BINDING_TABLE_POINTERS(const struct ilo_dev_info *dev,
uint32_t ps_binding_table,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x01);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_BINDING_TABLE_POINTERS);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(dev, 6, 6);
@ -604,7 +600,7 @@ gen6_emit_3DSTATE_SAMPLER_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t ps_sampler_state,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x02);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLER_STATE_POINTERS);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(dev, 6, 6);
@ -626,7 +622,7 @@ gen6_emit_3DSTATE_URB(const struct ilo_dev_info *dev,
int vs_entry_size, int gs_entry_size,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x05);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_URB);
const uint8_t cmd_len = 3;
const int row_size = 128; /* 1024 bits */
int vs_alloc_size, gs_alloc_size;
@ -671,7 +667,7 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info *dev,
const struct ilo_vb_state *vb,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x08);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS);
uint8_t cmd_len;
unsigned hw_idx;
@ -807,7 +803,7 @@ gen6_emit_3DSTATE_VERTEX_ELEMENTS(const struct ilo_dev_info *dev,
bool prepend_generated_ids,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x09);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS);
uint8_t cmd_len;
unsigned i;
@ -881,7 +877,7 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev,
bool enable_cut_index,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x0a);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER);
const uint8_t cmd_len = 3;
struct ilo_buffer *buf = ilo_buffer(ib->hw_resource);
uint32_t start_offset, end_offset;
@ -939,7 +935,7 @@ gen6_emit_3DSTATE_VIEWPORT_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t cc_viewport,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x0d);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(dev, 6, 6);
@ -962,7 +958,7 @@ gen6_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t color_calc_state,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x0e);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(dev, 6, 6);
@ -980,7 +976,7 @@ gen6_emit_3DSTATE_SCISSOR_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t scissor_rect,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x0f);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS);
const uint8_t cmd_len = 2;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -997,7 +993,7 @@ gen6_emit_3DSTATE_VS(const struct ilo_dev_info *dev,
int num_samplers,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x10);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VS);
const uint8_t cmd_len = 6;
const struct ilo_shader_cso *cso;
uint32_t dw2, dw4, dw5;
@ -1040,7 +1036,7 @@ gen6_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
int verts_per_prim,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_GS);
const uint8_t cmd_len = 7;
uint32_t dw1, dw2, dw4, dw5, dw6;
@ -1110,7 +1106,7 @@ gen6_emit_3DSTATE_CLIP(const struct ilo_dev_info *dev,
int num_viewports,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x12);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP);
const uint8_t cmd_len = 4;
uint32_t dw1, dw2, dw3;
@ -1157,7 +1153,7 @@ gen6_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
const struct ilo_shader_state *fs,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SF);
const uint8_t cmd_len = 20;
uint32_t payload_raster[6], payload_sbe[13];
@ -1185,7 +1181,7 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
uint32_t hiz_op,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_WM);
const uint8_t cmd_len = 9;
const int num_samples = 1;
const struct ilo_shader_cso *fs_cso;
@ -1300,7 +1296,7 @@ gen6_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x15);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_VS);
const uint8_t cmd_len = 5;
uint32_t buf_dw[4], buf_enabled;
@ -1331,7 +1327,7 @@ gen6_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x16);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_GS);
const uint8_t cmd_len = 5;
uint32_t buf_dw[4], buf_enabled;
@ -1362,7 +1358,7 @@ gen6_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x17);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS);
const uint8_t cmd_len = 5;
uint32_t buf_dw[4], buf_enabled;
@ -1392,7 +1388,7 @@ gen6_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
unsigned sample_mask,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK);
const uint8_t cmd_len = 2;
const unsigned valid_mask = 0xf;
@ -1412,7 +1408,7 @@ gen6_emit_3DSTATE_DRAWING_RECTANGLE(const struct ilo_dev_info *dev,
unsigned width, unsigned height,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x00);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE);
const uint8_t cmd_len = 4;
unsigned xmax = x + width - 1;
unsigned ymax = y + height - 1;
@ -1495,7 +1491,8 @@ gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint32_t cmd = (dev->gen >= ILO_GEN(7)) ?
ILO_GPE_CMD(0x3, 0x0, 0x05) : ILO_GPE_CMD(0x3, 0x1, 0x05);
GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
const uint8_t cmd_len = 7;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -1516,7 +1513,7 @@ gen6_emit_3DSTATE_POLY_STIPPLE_OFFSET(const struct ilo_dev_info *dev,
int x_offset, int y_offset,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x06);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_OFFSET);
const uint8_t cmd_len = 2;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -1534,7 +1531,7 @@ gen6_emit_3DSTATE_POLY_STIPPLE_PATTERN(const struct ilo_dev_info *dev,
const struct pipe_poly_stipple *pattern,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x07);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_PATTERN);
const uint8_t cmd_len = 33;
int i;
@ -1553,7 +1550,7 @@ gen6_emit_3DSTATE_LINE_STIPPLE(const struct ilo_dev_info *dev,
unsigned pattern, unsigned factor,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x08);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_LINE_STIPPLE);
const uint8_t cmd_len = 3;
unsigned inverse;
@ -1583,7 +1580,7 @@ static inline void
gen6_emit_3DSTATE_AA_LINE_PARAMETERS(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x0a);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -1602,7 +1599,7 @@ gen6_emit_3DSTATE_GS_SVB_INDEX(const struct ilo_dev_info *dev,
bool load_vertex_count,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x0b);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_GS_SVB_INDEX);
const uint8_t cmd_len = 4;
uint32_t dw1;
@ -1628,7 +1625,7 @@ gen6_emit_3DSTATE_MULTISAMPLE(const struct ilo_dev_info *dev,
bool pixel_location_center,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x0d);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE);
const uint8_t cmd_len = (dev->gen >= ILO_GEN(7)) ? 4 : 3;
uint32_t dw1, dw2, dw3;
@ -1678,8 +1675,8 @@ gen6_emit_3DSTATE_STENCIL_BUFFER(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint32_t cmd = (dev->gen >= ILO_GEN(7)) ?
ILO_GPE_CMD(0x3, 0x0, 0x06) :
ILO_GPE_CMD(0x3, 0x1, 0x0e);
GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -1698,8 +1695,8 @@ gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint32_t cmd = (dev->gen >= ILO_GEN(7)) ?
ILO_GPE_CMD(0x3, 0x0, 0x07) :
ILO_GPE_CMD(0x3, 0x1, 0x0f);
GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -1717,7 +1714,7 @@ gen6_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
uint32_t clear_val,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x10);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS);
const uint8_t cmd_len = 2;
ILO_GPE_VALID_GEN(dev, 6, 6);
@ -1736,7 +1733,7 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
bool write_qword,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x2, 0x00);
const uint32_t cmd = GEN6_RENDER_CMD(3D, PIPE_CONTROL);
const uint8_t cmd_len = (write_qword) ? 5 : 4;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
@ -1824,7 +1821,7 @@ gen6_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
bool rectlist,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DPRIMITIVE);
const uint8_t cmd_len = 6;
const int prim = (rectlist) ?
GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);

167
src/gallium/drivers/ilo/ilo_gpe_gen7.h
View File

@ -48,7 +48,7 @@ gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
uint32_t clear_val,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x04);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS);
const uint8_t cmd_len = 3;
ILO_GPE_VALID_GEN(dev, 7, 7.5);
@ -66,7 +66,7 @@ gen7_emit_3DSTATE_VF(const struct ilo_dev_info *dev,
uint32_t cut_index,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x0c);
const uint32_t cmd = GEN75_RENDER_CMD(3D, 3DSTATE_VF);
const uint8_t cmd_len = 2;
ILO_GPE_VALID_GEN(dev, 7.5, 7.5);
@ -83,7 +83,9 @@ gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
int subop, uint32_t pointer,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
GEN6_RENDER_SUBTYPE_3D |
subop;
const uint8_t cmd_len = 2;
ILO_GPE_VALID_GEN(dev, 7, 7.5);
@ -99,7 +101,8 @@ gen7_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t color_calc_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x0e, color_calc_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, color_calc_state, cp);
}
static inline void
@ -108,7 +111,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
int num_samplers,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x11);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_GS);
const uint8_t cmd_len = 7;
const struct ilo_shader_cso *cso;
uint32_t dw2, dw4, dw5;
@ -152,7 +155,7 @@ gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
enum pipe_format zs_format,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x13);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SF);
const uint8_t cmd_len = 7;
const int num_samples = 1;
uint32_t payload[6];
@ -176,7 +179,7 @@ gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
bool cc_may_kill, uint32_t hiz_op,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x14);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_WM);
const uint8_t cmd_len = 3;
const int num_samples = 1;
uint32_t dw1, dw2;
@ -224,7 +227,9 @@ gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
GEN6_RENDER_SUBTYPE_3D |
subop;
const uint8_t cmd_len = 7;
uint32_t dw[6];
int total_read_length, i;
@ -232,7 +237,9 @@ gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
ILO_GPE_VALID_GEN(dev, 7, 7.5);
/* VS, HS, DS, GS, and PS variants */
assert(subop >= 0x15 && subop <= 0x1a && subop != 0x18);
assert(subop >= GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS &&
subop <= GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS &&
subop != GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK);
assert(num_bufs <= 4);
@ -291,7 +298,8 @@ gen7_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(dev, 0x15, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
bufs, sizes, num_bufs, cp);
}
static inline void
@ -300,7 +308,8 @@ gen7_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(dev, 0x16, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS,
bufs, sizes, num_bufs, cp);
}
static inline void
@ -309,7 +318,8 @@ gen7_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(dev, 0x17, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
bufs, sizes, num_bufs, cp);
}
static inline void
@ -318,7 +328,7 @@ gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
int num_samples,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x18);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK);
const uint8_t cmd_len = 2;
const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
@ -347,7 +357,8 @@ gen7_emit_3DSTATE_CONSTANT_HS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(dev, 0x19, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS,
bufs, sizes, num_bufs, cp);
}
static inline void
@ -356,7 +367,8 @@ gen7_emit_3DSTATE_CONSTANT_DS(const struct ilo_dev_info *dev,
int num_bufs,
struct ilo_cp *cp)
{
gen7_emit_3dstate_constant(dev, 0x1a, bufs, sizes, num_bufs, cp);
gen7_emit_3dstate_constant(dev, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS,
bufs, sizes, num_bufs, cp);
}
static inline void
@ -365,7 +377,7 @@ gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
int num_samplers,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1b);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_HS);
const uint8_t cmd_len = 7;
ILO_GPE_VALID_GEN(dev, 7, 7.5);
@ -387,7 +399,7 @@ static inline void
gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1c);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_TE);
const uint8_t cmd_len = 4;
ILO_GPE_VALID_GEN(dev, 7, 7.5);
@ -406,7 +418,7 @@ gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
int num_samplers,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1d);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_DS);
const uint8_t cmd_len = 6;
ILO_GPE_VALID_GEN(dev, 7, 7.5);
@ -431,7 +443,7 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
bool rasterizer_discard,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1e);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_STREAMOUT);
const uint8_t cmd_len = 3;
const bool enable = (buffer_mask != 0);
uint32_t dw1, dw2;
@ -492,7 +504,7 @@ gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
const struct ilo_shader_state *fs,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x1f);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_SBE);
const uint8_t cmd_len = 14;
uint32_t dw[13];
@ -512,7 +524,7 @@ gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
int num_samplers, bool dual_blend,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, 0x20);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_PS);
const uint8_t cmd_len = 8;
const struct ilo_shader_cso *cso;
uint32_t dw2, dw4, dw5;
@ -579,7 +591,9 @@ gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(const struct ilo_dev_info *dev
uint32_t sf_clip_viewport,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x21, sf_clip_viewport, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
sf_clip_viewport, cp);
}
static inline void
@ -587,7 +601,9 @@ gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(const struct ilo_dev_info *dev,
uint32_t cc_viewport,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x23, cc_viewport, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
cc_viewport, cp);
}
static inline void
@ -595,7 +611,9 @@ gen7_emit_3DSTATE_BLEND_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t blend_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x24, blend_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS,
blend_state, cp);
}
static inline void
@ -603,7 +621,9 @@ gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(const struct ilo_dev_info *dev,
uint32_t depth_stencil_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x25, depth_stencil_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
depth_stencil_state, cp);
}
static inline void
@ -611,7 +631,9 @@ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x26, binding_table, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS,
binding_table, cp);
}
static inline void
@ -619,7 +641,9 @@ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x27, binding_table, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS,
binding_table, cp);
}
static inline void
@ -627,7 +651,9 @@ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x28, binding_table, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS,
binding_table, cp);
}
static inline void
@ -635,7 +661,9 @@ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x29, binding_table, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS,
binding_table, cp);
}
static inline void
@ -643,7 +671,9 @@ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(const struct ilo_dev_info *dev,
uint32_t binding_table,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x2a, binding_table, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS,
binding_table, cp);
}
static inline void
@ -651,7 +681,9 @@ gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x2b, sampler_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS,
sampler_state, cp);
}
static inline void
@ -659,7 +691,9 @@ gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_HS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x2c, sampler_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS,
sampler_state, cp);
}
static inline void
@ -667,7 +701,9 @@ gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_DS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x2d, sampler_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS,
sampler_state, cp);
}
static inline void
@ -675,7 +711,9 @@ gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_GS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x2e, sampler_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS,
sampler_state, cp);
}
static inline void
@ -683,7 +721,9 @@ gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(const struct ilo_dev_info *dev,
uint32_t sampler_state,
struct ilo_cp *cp)
{
gen7_emit_3dstate_pointer(dev, 0x2f, sampler_state, cp);
gen7_emit_3dstate_pointer(dev,
GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS,
sampler_state, cp);
}
static inline void
@ -692,7 +732,9 @@ gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
int entry_size,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x0, subop);
const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
GEN6_RENDER_SUBTYPE_3D |
subop;
const uint8_t cmd_len = 2;
const int row_size = 64; /* 512 bits */
int alloc_size, num_entries, min_entries, max_entries;
@ -700,7 +742,8 @@ gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
ILO_GPE_VALID_GEN(dev, 7, 7.5);
/* VS, HS, DS, and GS variants */
assert(subop >= 0x30 && subop <= 0x33);
assert(subop >= GEN7_RENDER_OPCODE_3DSTATE_URB_VS &&
subop <= GEN7_RENDER_OPCODE_3DSTATE_URB_GS);
/* in multiples of 8KB */
assert(offset % 8192 == 0);
@ -718,14 +761,14 @@ gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
* cause performance to decrease due to banking in the URB. Element
* sizes of 16 to 20 should be programmed with six 512-bit URB rows."
*/
if (subop == 0x30 && alloc_size == 5)
if (subop == GEN7_RENDER_OPCODE_3DSTATE_URB_VS && alloc_size == 5)
alloc_size = 6;
/* in multiples of 8 */
num_entries = (size / row_size / alloc_size) & ~7;
switch (subop) {
case 0x30: /* 3DSTATE_URB_VS */
case GEN7_RENDER_OPCODE_3DSTATE_URB_VS:
min_entries = 32;
switch (dev->gen) {
@ -742,16 +785,16 @@ gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
if (num_entries > max_entries)
num_entries = max_entries;
break;
case 0x31: /* 3DSTATE_URB_HS */
case GEN7_RENDER_OPCODE_3DSTATE_URB_HS:
max_entries = (dev->gt == 2) ? 64 : 32;
if (num_entries > max_entries)
num_entries = max_entries;
break;
case 0x32: /* 3DSTATE_URB_DS */
case GEN7_RENDER_OPCODE_3DSTATE_URB_DS:
if (num_entries)
assert(num_entries >= 138);
break;
case 0x33: /* 3DSTATE_URB_GS */
case GEN7_RENDER_OPCODE_3DSTATE_URB_GS:
switch (dev->gen) {
case ILO_GEN(7.5):
max_entries = (dev->gt >= 2) ? 640 : 256;
@ -782,7 +825,8 @@ gen7_emit_3DSTATE_URB_VS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(dev, 0x30, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_VS,
offset, size, entry_size, cp);
}
static inline void
@ -790,7 +834,8 @@ gen7_emit_3DSTATE_URB_HS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(dev, 0x31, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_HS,
offset, size, entry_size, cp);
}
static inline void
@ -798,7 +843,8 @@ gen7_emit_3DSTATE_URB_DS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(dev, 0x32, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_DS,
offset, size, entry_size, cp);
}
static inline void
@ -806,7 +852,8 @@ gen7_emit_3DSTATE_URB_GS(const struct ilo_dev_info *dev,
int offset, int size, int entry_size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_urb(dev, 0x33, offset, size, entry_size, cp);
gen7_emit_3dstate_urb(dev, GEN7_RENDER_OPCODE_3DSTATE_URB_GS,
offset, size, entry_size, cp);
}
static inline void
@ -814,14 +861,17 @@ gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
int subop, int offset, int size,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, subop);
const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
GEN6_RENDER_SUBTYPE_3D |
subop;
const uint8_t cmd_len = 2;
int end;
ILO_GPE_VALID_GEN(dev, 7, 7.5);
/* VS, HS, DS, GS, and PS variants */
assert(subop >= 0x12 && subop <= 0x16);
assert(subop >= GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS &&
subop <= GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS);
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 68:
@ -873,7 +923,8 @@ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(dev, 0x12, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev,
GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS, offset, size, cp);
}
static inline void
@ -881,7 +932,8 @@ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_HS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(dev, 0x13, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev,
GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_HS, offset, size, cp);
}
static inline void
@ -889,7 +941,8 @@ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_DS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(dev, 0x14, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev,
GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_DS, offset, size, cp);
}
static inline void
@ -897,7 +950,8 @@ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_GS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(dev, 0x15, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev,
GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_GS, offset, size, cp);
}
static inline void
@ -905,7 +959,8 @@ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(const struct ilo_dev_info *dev,
int offset, int size,
struct ilo_cp *cp)
{
gen7_emit_3dstate_push_constant_alloc(dev, 0x16, offset, size, cp);
gen7_emit_3dstate_push_constant_alloc(dev,
GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS, offset, size, cp);
}
static inline void
@ -913,7 +968,7 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
const struct pipe_stream_output_info *so_info,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x17);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_SO_DECL_LIST);
uint16_t cmd_len;
int buffer_selects, num_entries, i;
uint16_t so_decls[128];
@ -1005,7 +1060,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
const struct pipe_stream_output_target *so_target,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x1, 0x18);
const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER);
const uint8_t cmd_len = 4;
struct ilo_buffer *buf;
int end;
@ -1048,7 +1103,7 @@ gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
bool rectlist,
struct ilo_cp *cp)
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00);
const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DPRIMITIVE);
const uint8_t cmd_len = 7;
const int prim = (rectlist) ?
GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);