radeonsi: enable RGP on gfx10.3
It seems to work on VanGogh. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9492>
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@ -90,7 +90,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
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/* Select the first active CUs */
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/* Select the first active CUs */
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int first_active_cu = ffs(sctx->screen->info.cu_mask[se][0]);
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int first_active_cu = ffs(sctx->screen->info.cu_mask[se][0]);
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if (sctx->chip_class == GFX10) {
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if (sctx->chip_class >= GFX10) {
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/* Order seems important for the following 2 registers. */
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/* Order seems important for the following 2 registers. */
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radeon_set_privileged_config_reg(cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE,
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radeon_set_privileged_config_reg(cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE,
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S_008D04_SIZE(shifted_size) |
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S_008D04_SIZE(shifted_size) |
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@ -125,7 +125,9 @@ si_emit_thread_trace_start(struct si_context* sctx,
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S_008D1C_REG_STALL_EN(1) |
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S_008D1C_REG_STALL_EN(1) |
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S_008D1C_SPI_STALL_EN(1) |
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S_008D1C_SPI_STALL_EN(1) |
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S_008D1C_SQ_STALL_EN(1) |
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S_008D1C_SQ_STALL_EN(1) |
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S_008D1C_REG_DROP_ON_STALL(0));
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S_008D1C_REG_DROP_ON_STALL(0) |
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S_008D1C_LOWATER_OFFSET(
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sctx->chip_class >= GFX10_3 ? 4 : 0));
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} else {
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} else {
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/* Order seems important for the following 4 registers. */
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/* Order seems important for the following 4 registers. */
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radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2,
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radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2,
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@ -235,6 +237,7 @@ si_copy_thread_trace_info_regs(struct si_context* sctx,
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const uint32_t *thread_trace_info_regs = NULL;
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const uint32_t *thread_trace_info_regs = NULL;
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switch (sctx->chip_class) {
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switch (sctx->chip_class) {
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case GFX10_3:
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case GFX10:
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case GFX10:
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thread_trace_info_regs = gfx10_thread_trace_info_regs;
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thread_trace_info_regs = gfx10_thread_trace_info_regs;
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break;
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break;
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@ -298,7 +301,7 @@ si_emit_thread_trace_stop(struct si_context *sctx,
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S_030800_SH_INDEX(0) |
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S_030800_SH_INDEX(0) |
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S_030800_INSTANCE_BROADCAST_WRITES(1));
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S_030800_INSTANCE_BROADCAST_WRITES(1));
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if (sctx->chip_class == GFX10) {
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if (sctx->chip_class >= GFX10) {
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/* Make sure to wait for the trace buffer. */
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/* Make sure to wait for the trace buffer. */
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
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radeon_emit(cs, WAIT_REG_MEM_NOT_EQUAL); /* wait until the register is equal to the reference value */
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radeon_emit(cs, WAIT_REG_MEM_NOT_EQUAL); /* wait until the register is equal to the reference value */
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@ -559,7 +562,7 @@ si_init_thread_trace(struct si_context *sctx)
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return false;
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return false;
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}
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}
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if (sctx->chip_class > GFX10) {
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if (sctx->chip_class > GFX10_3) {
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fprintf(stderr, "radeonsi: Thread trace is not supported "
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fprintf(stderr, "radeonsi: Thread trace is not supported "
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"for that GPU!\n");
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"for that GPU!\n");
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return false;
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return false;
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@ -741,7 +744,7 @@ si_emit_spi_config_cntl(struct si_context* sctx,
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S_031100_ENABLE_SQG_TOP_EVENTS(enable) |
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S_031100_ENABLE_SQG_TOP_EVENTS(enable) |
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S_031100_ENABLE_SQG_BOP_EVENTS(enable);
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S_031100_ENABLE_SQG_BOP_EVENTS(enable);
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if (sctx->chip_class == GFX10)
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if (sctx->chip_class >= GFX10)
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spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3);
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spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3);
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radeon_set_uconfig_reg(cs, R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
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radeon_set_uconfig_reg(cs, R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
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