pan/midgard: Integrate LCRA
Pretty routine, we do have a hack to force swizzle alignment for !32-bit for until we implement !32-bit the right way. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig
Tomeu Vizoso
parent
66ad64d73d
commit
e343f2ceb9
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@ -27,6 +27,7 @@
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#include "midgard.h"
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#include "helpers.h"
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#include "midgard_compile.h"
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#include "lcra.h"
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#include "util/hash_table.h"
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#include "util/u_dynarray.h"
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@ -580,10 +581,6 @@ mir_has_arg(midgard_instruction *ins, unsigned arg)
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void schedule_program(compiler_context *ctx);
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/* Register allocation */
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struct ra_graph;
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/* Broad types of register classes so we can handle special
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* registers */
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@ -597,8 +594,8 @@ struct ra_graph;
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#define REG_CLASS_FRAGC 5
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void mir_lower_special_reads(compiler_context *ctx);
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struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
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void install_registers(compiler_context *ctx, struct ra_graph *g);
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struct lcra_state* allocate_registers(compiler_context *ctx, bool *spilled);
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void install_registers(compiler_context *ctx, struct lcra_state *g);
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void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
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void mir_compute_liveness(compiler_context *ctx);
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void mir_invalidate_liveness(compiler_context *ctx);
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@ -27,6 +27,7 @@
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#include "util/register_allocate.h"
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include "lcra.h"
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/* For work registers, we can subdivide in various ways. So we create
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* classes for the various sizes and conflict accordingly, keeping in
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@ -113,42 +114,26 @@ default_phys_reg(int reg, midgard_reg_mode size)
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* register corresponds to */
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static struct phys_reg
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index_to_reg(compiler_context *ctx, struct ra_graph *g, unsigned reg, midgard_reg_mode size)
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index_to_reg(compiler_context *ctx, struct lcra_state *l, unsigned reg, midgard_reg_mode size)
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{
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/* Check for special cases */
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if (reg == ~0)
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return default_phys_reg(REGISTER_UNUSED, size);
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else if (reg >= SSA_FIXED_MINIMUM)
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return default_phys_reg(SSA_REG_FROM_FIXED(reg), size);
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else if (!g)
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else if (!l)
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return default_phys_reg(REGISTER_UNUSED, size);
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/* Special cases aside, we pick the underlying register */
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int virt = ra_get_node_reg(g, reg);
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/* Divide out the register and classification */
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int phys = virt / WORK_STRIDE;
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int type = virt % WORK_STRIDE;
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/* Apply shadow registers */
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if (phys >= SHADOW_R28 && phys <= SHADOW_R29)
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phys += 28 - SHADOW_R28;
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else if (phys == SHADOW_R0)
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phys = 0;
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unsigned bytes = mir_bytes_for_mode(size);
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struct phys_reg r = {
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.reg = phys,
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.offset = __builtin_ctz(reg_type_to_mask[type]) * bytes,
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.size = bytes
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.reg = l->solutions[reg] / 16,
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.offset = l->solutions[reg] & 0xF,
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.size = mir_bytes_for_mode(size)
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};
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/* Report that we actually use this register, and return it */
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if (phys < 16)
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ctx->work_registers = MAX2(ctx->work_registers, phys);
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if (r.reg < 16)
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ctx->work_registers = MAX2(ctx->work_registers, r.reg);
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return r;
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}
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@ -525,7 +510,7 @@ mir_lower_special_reads(compiler_context *ctx)
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static void
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mir_compute_segment_interference(
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compiler_context *ctx,
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struct ra_graph *l,
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struct lcra_state *l,
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midgard_bundle *bun,
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unsigned pivot,
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unsigned i)
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@ -546,7 +531,9 @@ mir_compute_segment_interference(
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continue;
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}
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ra_add_node_interference(l, bun->instructions[q]->dest, bun->instructions[j]->src[s]);
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unsigned mask = mir_bytemask(bun->instructions[q]);
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unsigned rmask = mir_bytemask_of_read_components(bun->instructions[j], bun->instructions[j]->src[s]);
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lcra_add_node_interference(l, bun->instructions[q]->dest, mask, bun->instructions[j]->src[s], rmask);
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}
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}
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}
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@ -555,7 +542,7 @@ mir_compute_segment_interference(
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static void
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mir_compute_bundle_interference(
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compiler_context *ctx,
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struct ra_graph *l,
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struct lcra_state *l,
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midgard_bundle *bun)
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{
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if (!IS_ALU(bun->tag))
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@ -580,7 +567,8 @@ mir_compute_bundle_interference(
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static void
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mir_compute_interference(
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compiler_context *ctx,
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struct ra_graph *g)
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struct ra_graph *g,
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struct lcra_state *l)
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{
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/* First, we need liveness information to be computed per block */
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mir_compute_liveness(ctx);
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@ -600,8 +588,10 @@ mir_compute_interference(
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if (dest < ctx->temp_count) {
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for (unsigned i = 0; i < ctx->temp_count; ++i)
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if (live[i])
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ra_add_node_interference(g, dest, i);
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if (live[i]) {
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unsigned mask = mir_bytemask(ins);
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lcra_add_node_interference(l, dest, mask, i, live[i]);
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}
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}
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/* Update live_in */
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@ -609,7 +599,7 @@ mir_compute_interference(
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}
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mir_foreach_bundle_in_block(blk, bun)
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mir_compute_bundle_interference(ctx, g, bun);
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mir_compute_bundle_interference(ctx, l, bun);
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free(live);
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}
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@ -618,7 +608,7 @@ mir_compute_interference(
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/* This routine performs the actual register allocation. It should be succeeded
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* by install_registers */
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struct ra_graph *
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struct lcra_state *
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allocate_registers(compiler_context *ctx, bool *spilled)
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{
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/* The number of vec4 work registers available depends on when the
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@ -644,6 +634,21 @@ allocate_registers(compiler_context *ctx, bool *spilled)
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* size (vec2/vec3..). First, we'll go through and determine the
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* minimum size needed to hold values */
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struct lcra_state *l = lcra_alloc_equations(ctx->temp_count, 1, 8, 16, 5);
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/* Starts of classes, in bytes */
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l->class_start[REG_CLASS_WORK] = 16 * 0;
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l->class_start[REG_CLASS_LDST] = 16 * 26;
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l->class_start[REG_CLASS_TEXR] = 16 * 28;
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l->class_start[REG_CLASS_TEXW] = 16 * 28;
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l->class_size[REG_CLASS_WORK] = 16 * work_count;
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l->class_size[REG_CLASS_LDST] = 16 * 2;
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l->class_size[REG_CLASS_TEXR] = 16 * 2;
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l->class_size[REG_CLASS_TEXW] = 16 * 2;
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lcra_set_disjoint_class(l, REG_CLASS_TEXR, REG_CLASS_TEXW);
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unsigned *found_class = calloc(sizeof(unsigned), ctx->temp_count);
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mir_foreach_instr_global(ctx, ins) {
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@ -657,8 +662,17 @@ allocate_registers(compiler_context *ctx, bool *spilled)
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int dest = ins->dest;
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found_class[dest] = MAX2(found_class[dest], class);
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lcra_set_alignment(l, dest, 2); /* (1 << 2) = 4 */
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/* XXX: Ensure swizzles align the right way with more LCRA constraints? */
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if (ins->type == TAG_ALU_4 && ins->alu.reg_mode != midgard_reg_mode_32)
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lcra_set_alignment(l, dest, 3); /* (1 << 3) = 8 */
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}
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for (unsigned i = 0; i < ctx->temp_count; ++i)
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lcra_restrict_range(l, i, (found_class[i] + 1) * 4);
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/* Next, we'll determine semantic class. We default to zero (work).
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* But, if we're used with a special operation, that will force us to a
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* particular class. Each node must be assigned to exactly one class; a
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@ -681,6 +695,8 @@ allocate_registers(compiler_context *ctx, bool *spilled)
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force_vec4(found_class, ins->src[0]);
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force_vec4(found_class, ins->src[1]);
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force_vec4(found_class, ins->src[2]);
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lcra_restrict_range(l, ins->dest, 16);
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}
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} else if (ins->type == TAG_TEXTURE_4) {
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set_class(found_class, ins->dest, REG_CLASS_TEXW);
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@ -700,27 +716,21 @@ allocate_registers(compiler_context *ctx, bool *spilled)
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/* Mark writeout to r0 */
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mir_foreach_instr_global(ctx, ins) {
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if (ins->compact_branch && ins->writeout)
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set_class(found_class, ins->src[0], REG_CLASS_FRAGC);
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if (ins->compact_branch && ins->writeout && ins->src[0] < ctx->temp_count)
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l->solutions[ins->src[0]] = 0;
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}
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for (unsigned i = 0; i < ctx->temp_count; ++i) {
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unsigned class = found_class[i];
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l->class[i] = (class >> 2);
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ra_set_node_class(g, i, classes[class]);
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}
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mir_compute_interference(ctx, g);
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mir_compute_interference(ctx, g, l);
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if (!ra_allocate(g)) {
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*spilled = true;
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} else {
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*spilled = false;
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}
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/* Whether we were successful or not, report the graph so we can
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* compute spill nodes */
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return g;
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*spilled = !lcra_solve(l);
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return l;
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}
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/* Once registers have been decided via register allocation
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@ -730,7 +740,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
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static void
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install_registers_instr(
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compiler_context *ctx,
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struct ra_graph *g,
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struct lcra_state *l,
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midgard_instruction *ins)
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{
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switch (ins->type) {
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@ -741,9 +751,9 @@ install_registers_instr(
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if (ins->compact_branch)
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return;
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struct phys_reg src1 = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
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struct phys_reg src2 = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
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struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
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struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
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struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
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mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
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@ -789,13 +799,13 @@ install_registers_instr(
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bool encodes_src = OP_IS_STORE(ins->load_store.op);
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if (encodes_src) {
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struct phys_reg src = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
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struct phys_reg src = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
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assert(src.reg == 26 || src.reg == 27);
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ins->load_store.reg = src.reg - 26;
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offset_swizzle(ins->swizzle[0], src.offset, src.size, 0);
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} else {
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struct phys_reg dst = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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struct phys_reg dst = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
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ins->load_store.reg = dst.reg;
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offset_swizzle(ins->swizzle[0], 0, 4, dst.offset);
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@ -808,14 +818,14 @@ install_registers_instr(
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unsigned src3 = ins->src[2];
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if (src2 != ~0) {
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struct phys_reg src = index_to_reg(ctx, g, src2, mir_srcsize(ins, 1));
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struct phys_reg src = index_to_reg(ctx, l, src2, mir_srcsize(ins, 1));
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unsigned component = src.offset / src.size;
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assert(component * src.size == src.offset);
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ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
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}
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if (src3 != ~0) {
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struct phys_reg src = index_to_reg(ctx, g, src3, mir_srcsize(ins, 2));
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struct phys_reg src = index_to_reg(ctx, l, src3, mir_srcsize(ins, 2));
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unsigned component = src.offset / src.size;
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assert(component * src.size == src.offset);
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ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
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@ -826,9 +836,9 @@ install_registers_instr(
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case TAG_TEXTURE_4: {
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/* Grab RA results */
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struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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struct phys_reg coord = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
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struct phys_reg lod = index_to_reg(ctx, g, ins->src[2], mir_srcsize(ins, 2));
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struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
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struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
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struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], mir_srcsize(ins, 2));
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assert(dest.reg == 28 || dest.reg == 29);
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assert(coord.reg == 28 || coord.reg == 29);
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@ -869,8 +879,8 @@ install_registers_instr(
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}
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void
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install_registers(compiler_context *ctx, struct ra_graph *g)
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install_registers(compiler_context *ctx, struct lcra_state *l)
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{
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mir_foreach_instr_global(ctx, ins)
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install_registers_instr(ctx, g, ins);
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install_registers_instr(ctx, l, ins);
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}
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@ -1187,7 +1187,7 @@ v_load_store_scratch(
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static void mir_spill_register(
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compiler_context *ctx,
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struct ra_graph *g,
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struct lcra_state *l,
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unsigned *spill_count)
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{
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unsigned spill_index = ctx->temp_count;
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@ -1197,7 +1197,7 @@ static void mir_spill_register(
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* nodes written to from an unspill */
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for (unsigned i = 0; i < ctx->temp_count; ++i) {
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ra_set_node_spill_cost(g, i, 1.0);
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lcra_set_node_spill_cost(l, i, 1);
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}
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/* We can't spill any bundles that contain unspills. This could be
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@ -1218,7 +1218,7 @@ static void mir_spill_register(
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unsigned src = bun->instructions[i]->src[s];
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if (src < ctx->temp_count)
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ra_set_node_spill_cost(g, src, -1.0);
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lcra_set_node_spill_cost(l, src, -1);
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}
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}
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}
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@ -1229,12 +1229,12 @@ static void mir_spill_register(
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for (unsigned i = 0; i < bun->instruction_count; ++i) {
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unsigned dest = bun->instructions[i]->dest;
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if (dest < ctx->temp_count)
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ra_set_node_spill_cost(g, dest, -1.0);
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lcra_set_node_spill_cost(l, dest, -1);
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}
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}
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}
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int spill_node = ra_get_best_spill_node(g);
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int spill_node = lcra_get_best_spill_node(l);
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if (spill_node < 0) {
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mir_print_shader(ctx);
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@ -1245,9 +1245,8 @@ static void mir_spill_register(
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* legitimately spill to TLS, but special registers just spill to work
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* registers */
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unsigned class = ra_get_node_class(g, spill_node);
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bool is_special = (class >> 2) != REG_CLASS_WORK;
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bool is_special_w = (class >> 2) == REG_CLASS_TEXW;
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bool is_special = l->class[spill_node] != REG_CLASS_WORK;
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bool is_special_w = l->class[spill_node] == REG_CLASS_TEXW;
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/* Allocate TLS slot (maybe) */
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unsigned spill_slot = !is_special ? (*spill_count)++ : 0;
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@ -1373,7 +1372,7 @@ static void mir_spill_register(
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void
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schedule_program(compiler_context *ctx)
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{
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struct ra_graph *g = NULL;
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struct lcra_state *l = NULL;
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bool spilled = false;
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int iter_count = 1000; /* max iterations */
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@ -1398,13 +1397,13 @@ schedule_program(compiler_context *ctx)
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do {
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if (spilled)
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mir_spill_register(ctx, g, &spill_count);
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mir_spill_register(ctx, l, &spill_count);
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mir_squeeze_index(ctx);
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mir_invalidate_liveness(ctx);
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g = NULL;
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g = allocate_registers(ctx, &spilled);
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l = NULL;
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l = allocate_registers(ctx, &spilled);
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} while(spilled && ((iter_count--) > 0));
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if (iter_count <= 0) {
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@ -1417,5 +1416,5 @@ schedule_program(compiler_context *ctx)
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|
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ctx->tls_size = spill_count * 16;
|
||||
|
||||
install_registers(ctx, g);
|
||||
install_registers(ctx, l);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue