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i965: Devirtualize update_renderbuffer_surface. 

Replace piles of my own boilerplate with 1-2 lines of code.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Kenneth Graunke 2017-08-17 01:05:31 -07:00
parent 081c54099c
commit e2dab867ac
4 changed files with 5 additions and 30 deletions
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4
src/mesa/drivers/dri/i965/brw_context.c
View File

@ -882,16 +882,12 @@ brwCreateContext(gl_api api,
brw->gs.base.stage = MESA_SHADER_GEOMETRY;
brw->wm.base.stage = MESA_SHADER_FRAGMENT;
if (brw->gen >= 8) {
gen6_init_vtable_surface_functions(brw);
brw->vtbl.emit_depth_stencil_hiz = gen8_emit_depth_stencil_hiz;
} else if (brw->gen >= 7) {
gen6_init_vtable_surface_functions(brw);
brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
} else if (brw->gen >= 6) {
gen6_init_vtable_surface_functions(brw);
brw->vtbl.emit_depth_stencil_hiz = gen6_emit_depth_stencil_hiz;
} else {
gen4_init_vtable_surface_functions(brw);
brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
}

5
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -633,11 +633,6 @@ struct brw_context
struct
{
uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
struct gl_renderbuffer *rb,
unsigned unit,
uint32_t surf_index);
/**
* Send the appropriate state packets to configure depth, stencil, and
* HiZ buffers (i965+ only)

4
src/mesa/drivers/dri/i965/brw_state.h
View File

@ -195,7 +195,6 @@ void *brw_state_batch(struct brw_context *brw,
uint32_t brw_state_batch_size(struct brw_context *brw, uint32_t offset);
/* brw_wm_surface_state.c */
void gen4_init_vtable_surface_functions(struct brw_context *brw);
uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
enum isl_format brw_isl_format_for_mesa_format(mesa_format mesa_format);
@ -247,9 +246,6 @@ void brw_emit_sampler_state(struct brw_context *brw,
bool non_normalized_coordinates,
uint32_t border_color_offset);
/* gen6_surface_state.c */
void gen6_init_vtable_surface_functions(struct brw_context *brw);
/* brw_vs_surface_state.c */
void
brw_upload_pull_constants(struct brw_context *brw,

22
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@ -1000,11 +1000,12 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw,
if (fb->_NumColorDrawBuffers >= 1) {
for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
const uint32_t surf_index = render_target_start + i;
struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[i];
if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) {
surf_offset[surf_index] =
brw->vtbl.update_renderbuffer_surface(
brw, fb->_ColorDrawBuffers[i], i, surf_index);
if (intel_renderbuffer(rb)) {
surf_offset[surf_index] = brw->gen >= 6 ?
gen6_update_renderbuffer_surface(brw, rb, i, surf_index) :
gen4_update_renderbuffer_surface(brw, rb, i, surf_index);
} else {
emit_null_surface_state(brw, w, h, s, &surf_offset[surf_index]);
}
@ -1669,19 +1670,6 @@ const struct brw_tracked_state brw_wm_image_surfaces = {
.emit = brw_upload_wm_image_surfaces,
};
void
gen4_init_vtable_surface_functions(struct brw_context *brw)
{
brw->vtbl.update_renderbuffer_surface = gen4_update_renderbuffer_surface;
}
void
gen6_init_vtable_surface_functions(struct brw_context *brw)
{
gen4_init_vtable_surface_functions(brw);
brw->vtbl.update_renderbuffer_surface = gen6_update_renderbuffer_surface;
}
static void
brw_upload_cs_work_groups_surface(struct brw_context *brw)
{