radv: Merge vtx_reuse_depth computation with PM4 generation.
Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
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@ -2860,8 +2860,13 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
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if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
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if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
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return;
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return;
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unsigned vtx_reuse_depth = 30;
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if (radv_pipeline_has_tess(pipeline) &&
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radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
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vtx_reuse_depth = 14;
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}
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radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
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radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
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pipeline->graphics.vtx_reuse_depth);
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S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
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}
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}
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static void
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static void
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@ -3178,12 +3183,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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pipeline->graphics.vtx_emit_num = 2;
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pipeline->graphics.vtx_emit_num = 2;
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}
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}
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pipeline->graphics.vtx_reuse_depth = 30;
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if (radv_pipeline_has_tess(pipeline) &&
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radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
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pipeline->graphics.vtx_reuse_depth = 14;
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}
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if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
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if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
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radv_dump_pipeline_stats(device, pipeline);
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radv_dump_pipeline_stats(device, pipeline);
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}
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}
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@ -1246,7 +1246,6 @@ struct radv_pipeline {
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bool ia_switch_on_eoi;
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bool ia_switch_on_eoi;
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bool partial_vs_wave;
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bool partial_vs_wave;
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uint8_t vtx_emit_num;
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uint8_t vtx_emit_num;
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uint32_t vtx_reuse_depth;
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struct radv_prim_vertex_count prim_vertex_count;
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struct radv_prim_vertex_count prim_vertex_count;
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bool can_use_guardband;
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bool can_use_guardband;
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uint32_t pa_sc_cliprect_rule;
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uint32_t pa_sc_cliprect_rule;
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