turnip: Ignore aspectMask for D32S8 framebuffer attachment
Vulkan spec says: "When an image view of a depth/stencil image is used as a depth/stencil framebuffer attachment, the aspectMask is ignored and both depth and stencil image subresources are used." Since we use two planes for D32S8 format we have to add a special case for depth in addition to already existing case for stencil. Fixes hang in CTS: dEQP-VK.renderpass.depth_stencil_write_conditions.stencil_kill_write_d32sf_s8ui Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15532>
This commit is contained in:
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72716993b2
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e255305e84
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@ -161,6 +161,24 @@ r2d_src(struct tu_cmd_buffer *cmd,
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tu_cs_image_flag_ref(cs, iview, layer);
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}
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static void
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r2d_src_depth(struct tu_cmd_buffer *cmd,
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struct tu_cs *cs,
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const struct tu_image_view *iview,
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uint32_t layer,
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VkFilter filter)
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{
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_INFO, 5);
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tu_cs_emit(cs, tu_image_view_depth(iview, SP_PS_2D_SRC_INFO));
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tu_cs_emit(cs, iview->view.SP_PS_2D_SRC_SIZE);
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tu_cs_emit_qw(cs, iview->depth_base_addr + iview->depth_layer_size * layer);
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/* SP_PS_2D_SRC_PITCH has shifted pitch field */
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tu_cs_emit(cs, iview->depth_PITCH << 9);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_FLAGS, 3);
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tu_cs_image_flag_ref(cs, &iview->view, layer);
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}
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static void
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r2d_src_stencil(struct tu_cmd_buffer *cmd,
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struct tu_cs *cs,
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@ -208,6 +226,18 @@ r2d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer)
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tu_cs_image_flag_ref(cs, iview, layer);
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}
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static void
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r2d_dst_depth(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
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{
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_INFO, 4);
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tu_cs_emit(cs, tu_image_view_depth(iview, RB_2D_DST_INFO));
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tu_cs_emit_qw(cs, iview->depth_base_addr + iview->depth_layer_size * layer);
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tu_cs_emit(cs, iview->depth_PITCH);
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS, 3);
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tu_cs_image_flag_ref(cs, &iview->view, layer);
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}
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static void
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r2d_dst_stencil(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
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{
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@ -950,6 +980,20 @@ r3d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer)
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tu_cs_emit_regs(cs, A6XX_RB_RENDER_CNTL(.flag_mrts = iview->ubwc_enabled));
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}
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static void
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r3d_dst_depth(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
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{
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(0), 6);
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tu_cs_emit(cs, tu_image_view_depth(iview, RB_MRT_BUF_INFO));
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tu_cs_image_depth_ref(cs, iview, layer);
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tu_cs_emit(cs, 0);
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(0), 3);
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tu_cs_image_flag_ref(cs, &iview->view, layer);
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tu_cs_emit_regs(cs, A6XX_RB_RENDER_CNTL(.flag_mrts = iview->view.ubwc_enabled));
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}
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static void
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r3d_dst_stencil(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
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{
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@ -1105,6 +1149,8 @@ struct blit_ops {
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uint64_t va, uint32_t pitch,
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uint32_t width, uint32_t height);
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void (*dst)(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer);
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void (*dst_depth)(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
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void (*dst_stencil)(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
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void (*dst_buffer)(struct tu_cs *cs, enum pipe_format format, uint64_t va, uint32_t pitch);
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void (*setup)(struct tu_cmd_buffer *cmd,
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struct tu_cs *cs,
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@ -1125,6 +1171,8 @@ static const struct blit_ops r2d_ops = {
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.src = r2d_src,
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.src_buffer = r2d_src_buffer,
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.dst = r2d_dst,
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.dst_depth = r2d_dst_depth,
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.dst_stencil = r2d_dst_stencil,
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.dst_buffer = r2d_dst_buffer,
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.setup = r2d_setup,
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.run = r2d_run,
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@ -1137,6 +1185,8 @@ static const struct blit_ops r3d_ops = {
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.src = r3d_src,
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.src_buffer = r3d_src_buffer,
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.dst = r3d_dst,
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.dst_depth = r3d_dst_depth,
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.dst_stencil = r3d_dst_stencil,
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.dst_buffer = r3d_dst_buffer,
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.setup = r3d_setup,
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.run = r3d_run,
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@ -2031,7 +2081,7 @@ resolve_sysmem(struct tu_cmd_buffer *cmd,
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uint32_t layer_mask,
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uint32_t layers,
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const VkRect2D *rect,
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bool separate_stencil)
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bool separate_ds)
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{
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const struct blit_ops *ops = &r2d_ops;
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@ -2043,9 +2093,14 @@ resolve_sysmem(struct tu_cmd_buffer *cmd,
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ops->coords(cs, &rect->offset, &rect->offset, &rect->extent);
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for_each_layer(i, layer_mask, layers) {
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if (separate_stencil) {
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r2d_src_stencil(cmd, cs, src, i, VK_FILTER_NEAREST);
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r2d_dst_stencil(cs, dst, i);
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if (separate_ds) {
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if (format == VK_FORMAT_D32_SFLOAT) {
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r2d_src_depth(cmd, cs, src, i, VK_FILTER_NEAREST);
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ops->dst_depth(cs, dst, i);
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} else {
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r2d_src_stencil(cmd, cs, src, i, VK_FILTER_NEAREST);
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ops->dst_stencil(cs, dst, i);
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}
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} else {
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ops->src(cmd, cs, &src->view, i, VK_FILTER_NEAREST);
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ops->dst(cs, &dst->view, i);
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@ -2071,7 +2126,7 @@ tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
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if (dst->image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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resolve_sysmem(cmd, cs, VK_FORMAT_D32_SFLOAT,
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src, dst, layer_mask, layers, rect, false);
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src, dst, layer_mask, layers, rect, true);
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resolve_sysmem(cmd, cs, VK_FORMAT_S8_UINT,
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src, dst, layer_mask, layers, rect, true);
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} else {
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@ -2556,7 +2611,7 @@ clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
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VkImageAspectFlags clear_mask,
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const VkRenderPassBeginInfo *info,
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uint32_t a,
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bool separate_stencil)
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bool separate_ds)
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{
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enum pipe_format format = tu_vk_format_to_pipe_format(vk_format);
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const struct tu_framebuffer *fb = cmd->state.framebuffer;
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@ -2574,11 +2629,12 @@ clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
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ops->clear_value(cs, format, &info->pClearValues[a]);
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for_each_layer(i, clear_views, fb->layers) {
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if (separate_stencil) {
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if (ops == &r3d_ops)
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r3d_dst_stencil(cs, iview, i);
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else
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r2d_dst_stencil(cs, iview, i);
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if (separate_ds) {
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if (vk_format == VK_FORMAT_D32_SFLOAT) {
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ops->dst_depth(cs, iview, i);
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} else {
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ops->dst_stencil(cs, iview, i);
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}
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} else {
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ops->dst(cs, &iview->view, i);
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}
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@ -2607,7 +2663,7 @@ tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
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if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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if (attachment->clear_mask & VK_IMAGE_ASPECT_DEPTH_BIT) {
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clear_sysmem_attachment(cmd, cs, VK_FORMAT_D32_SFLOAT, VK_IMAGE_ASPECT_COLOR_BIT,
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info, a, false);
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info, a, true);
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}
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if (attachment->clear_mask & VK_IMAGE_ASPECT_STENCIL_BIT) {
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clear_sysmem_attachment(cmd, cs, VK_FORMAT_S8_UINT, VK_IMAGE_ASPECT_COLOR_BIT,
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@ -2675,13 +2731,25 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
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vk_format_is_depth_or_stencil(attachment->format)));
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4);
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if (separate_stencil) {
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tu_cs_emit(cs, tu_image_view_stencil(iview, RB_BLIT_DST_INFO) & ~A6XX_RB_BLIT_DST_INFO_FLAGS);
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tu_cs_emit_qw(cs, iview->stencil_base_addr);
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tu_cs_emit(cs, iview->stencil_PITCH);
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if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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if (!separate_stencil) {
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tu_cs_emit(cs, tu_image_view_depth(iview, RB_BLIT_DST_INFO));
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tu_cs_emit_qw(cs, iview->depth_base_addr);
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tu_cs_emit(cs, iview->depth_PITCH);
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tu_cs_emit_regs(cs,
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A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset_stencil));
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
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tu_cs_image_flag_ref(cs, &iview->view, 0);
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tu_cs_emit_regs(cs,
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A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
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} else {
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tu_cs_emit(cs, tu_image_view_stencil(iview, RB_BLIT_DST_INFO) & ~A6XX_RB_BLIT_DST_INFO_FLAGS);
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tu_cs_emit_qw(cs, iview->stencil_base_addr);
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tu_cs_emit(cs, iview->stencil_PITCH);
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tu_cs_emit_regs(cs,
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A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset_stencil));
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}
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} else {
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tu_cs_emit(cs, iview->view.RB_BLIT_DST_INFO);
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tu_cs_image_ref_2d(cs, &iview->view, 0, false);
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@ -2764,10 +2832,16 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
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{
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r2d_setup_common(cmd, cs, format, VK_IMAGE_ASPECT_COLOR_BIT, 0, false,
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iview->view.ubwc_enabled, true);
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if (separate_stencil)
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r2d_dst_stencil(cs, iview, 0);
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else
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if (iview->image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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if (!separate_stencil) {
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r2d_dst_depth(cs, iview, 0);
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} else {
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r2d_dst_stencil(cs, iview, 0);
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}
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} else {
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r2d_dst(cs, &iview->view, 0);
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}
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tu_cs_emit_regs(cs,
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A6XX_SP_PS_2D_SRC_INFO(
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@ -2816,10 +2890,15 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
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r3d_coords(cs, &render_area->offset, &render_area->offset, &render_area->extent);
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if (separate_stencil)
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r3d_dst_stencil(cs, iview, 0);
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else
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if (iview->image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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if (!separate_stencil) {
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r3d_dst_depth(cs, iview, 0);
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} else {
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r3d_dst_stencil(cs, iview, 0);
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}
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} else {
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r3d_dst(cs, &iview->view, 0);
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}
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r3d_src_gmem(cmd, cs, iview, format, gmem_offset, cpp);
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@ -233,7 +233,10 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd,
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
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tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt).value);
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tu_cs_image_ref(cs, &iview->view, 0);
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if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
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tu_cs_image_depth_ref(cs, iview, 0);
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else
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tu_cs_image_ref(cs, &iview->view, 0);
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tu_cs_emit(cs, attachment->gmem_offset);
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tu_cs_emit_regs(cs,
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@ -135,6 +135,14 @@ tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uin
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tu_cs_emit_qw(cs, iview->stencil_base_addr + iview->stencil_layer_size * layer);
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}
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void
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tu_cs_image_depth_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
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{
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tu_cs_emit(cs, iview->depth_PITCH);
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tu_cs_emit(cs, iview->depth_layer_size >> 6);
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tu_cs_emit_qw(cs, iview->depth_base_addr + iview->depth_layer_size * layer);
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}
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void
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tu_cs_image_ref_2d(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, bool src)
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{
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@ -243,7 +251,13 @@ tu_image_view_init(struct tu_image_view *iview,
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fdl6_view_init(&iview->view, layouts, &args, has_z24uint_s8uint);
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if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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struct fdl_layout *layout = &image->layout[1];
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struct fdl_layout *layout = &image->layout[0];
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iview->depth_base_addr = image->iova +
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fdl_surface_offset(layout, range->baseMipLevel, range->baseArrayLayer);
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iview->depth_layer_size = fdl_layer_stride(layout, range->baseMipLevel);
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iview->depth_PITCH = A6XX_RB_DEPTH_BUFFER_PITCH(fdl_pitch(layout, range->baseMipLevel)).value;
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layout = &image->layout[1];
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iview->stencil_base_addr = image->iova +
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fdl_surface_offset(layout, range->baseMipLevel, range->baseArrayLayer);
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iview->stencil_layer_size = fdl_layer_stride(layout, range->baseMipLevel);
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@ -1585,6 +1585,11 @@ struct tu_image_view
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struct fdl6_view view;
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/* for d32s8 separate depth */
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uint64_t depth_base_addr;
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uint32_t depth_layer_size;
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uint32_t depth_PITCH;
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/* for d32s8 separate stencil */
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uint64_t stencil_base_addr;
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uint32_t stencil_layer_size;
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@ -1621,9 +1626,15 @@ tu_cs_image_flag_ref(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t l
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void
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tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
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void
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tu_cs_image_depth_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
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#define tu_image_view_stencil(iview, x) \
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((iview->view.x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
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#define tu_image_view_depth(iview, x) \
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((iview->view.x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_32_FLOAT))
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VkResult
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tu_gralloc_info(struct tu_device *device,
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const VkNativeBufferANDROID *gralloc_info,
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