radeonsi: add VS epilog
It only exports the primitive ID. Also used by TES when it's compiled as VS. The VS input location of the primitive ID input is v2. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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70de433dea
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e1b21696a3
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@ -540,7 +540,7 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
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struct si_screen *sscreen = (struct si_screen *)pscreen;
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struct si_shader_part *parts[] = {
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sscreen->vs_prologs,
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/* this will be filled with other shader parts */
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sscreen->vs_epilogs,
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};
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unsigned i;
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@ -90,6 +90,7 @@ struct si_screen {
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pipe_mutex shader_parts_mutex;
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struct si_shader_part *vs_prologs;
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struct si_shader_part *vs_epilogs;
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};
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struct si_blend_color {
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@ -129,6 +129,10 @@ static void si_init_shader_ctx(struct si_shader_context *ctx,
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LLVMTargetMachineRef tm,
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struct tgsi_shader_info *info);
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/* The VS location of the PrimitiveID input is the same in the epilog,
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* so that the main shader part doesn't have to move it.
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*/
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#define VS_EPILOG_PRIMID_LOC 2
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#define PERSPECTIVE_BASE 0
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#define LINEAR_BASE 9
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@ -2230,16 +2234,26 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
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"");
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}
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/* Export PrimitiveID when PS needs it. */
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if (si_vs_exports_prim_id(ctx->shader)) {
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outputs[i].name = TGSI_SEMANTIC_PRIMID;
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outputs[i].sid = 0;
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outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
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get_primitive_id(bld_base, 0));
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outputs[i].values[1] = bld_base->base.undef;
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outputs[i].values[2] = bld_base->base.undef;
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outputs[i].values[3] = bld_base->base.undef;
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i++;
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if (ctx->is_monolithic) {
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/* Export PrimitiveID when PS needs it. */
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if (si_vs_exports_prim_id(ctx->shader)) {
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outputs[i].name = TGSI_SEMANTIC_PRIMID;
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outputs[i].sid = 0;
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outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
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get_primitive_id(bld_base, 0));
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outputs[i].values[1] = bld_base->base.undef;
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outputs[i].values[2] = bld_base->base.undef;
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outputs[i].values[3] = bld_base->base.undef;
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i++;
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}
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} else {
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/* Return the primitive ID from the LLVM function. */
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ctx->return_value =
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LLVMBuildInsertValue(gallivm->builder,
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ctx->return_value,
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bitcast(bld_base, TGSI_TYPE_FLOAT,
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get_primitive_id(bld_base, 0)),
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VS_EPILOG_PRIMID_LOC, "");
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}
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si_llvm_export_vs(bld_base, outputs, i);
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@ -3724,6 +3738,11 @@ static void create_function(struct si_shader_context *ctx)
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for (i = 0; i < shader->selector->info.num_inputs; i++)
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params[num_params++] = ctx->i32;
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/* PrimitiveID output. */
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if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
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for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
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returns[num_returns++] = ctx->f32;
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}
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break;
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@ -3758,6 +3777,11 @@ static void create_function(struct si_shader_context *ctx)
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params[ctx->param_tes_v = num_params++] = ctx->f32;
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params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
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params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
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/* PrimitiveID output. */
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if (!ctx->is_monolithic && !shader->key.tes.as_es)
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for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
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returns[num_returns++] = ctx->f32;
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break;
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case TGSI_PROCESSOR_GEOMETRY:
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@ -4864,6 +4888,111 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen,
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return status;
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}
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/**
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* Compile the vertex shader epilog. This is also used by the tessellation
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* evaluation shader compiled as VS.
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*
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* The input is PrimitiveID.
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*
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* If PrimitiveID is required by the pixel shader, export it.
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* Otherwise, do nothing.
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*/
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static bool si_compile_vs_epilog(struct si_screen *sscreen,
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LLVMTargetMachineRef tm,
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struct pipe_debug_callback *debug,
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struct si_shader_part *out)
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{
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union si_shader_part_key *key = &out->key;
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struct si_shader_context ctx;
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struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
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struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
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LLVMTypeRef params[5];
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int num_params, i;
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bool status = true;
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si_init_shader_ctx(&ctx, sscreen, NULL, tm, NULL);
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ctx.type = TGSI_PROCESSOR_VERTEX;
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/* Declare input VGPRs. */
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num_params = key->vs_epilog.states.export_prim_id ?
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(VS_EPILOG_PRIMID_LOC + 1) : 0;
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assert(num_params <= ARRAY_SIZE(params));
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for (i = 0; i < num_params; i++)
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params[i] = ctx.f32;
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/* Create the function. */
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si_create_function(&ctx, NULL, 0, params, num_params,
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-1, -1);
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/* Emit exports. */
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if (key->vs_epilog.states.export_prim_id) {
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struct lp_build_context *base = &bld_base->base;
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struct lp_build_context *uint = &bld_base->uint_bld;
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LLVMValueRef args[9];
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args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
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args[1] = uint->zero; /* whether the EXEC mask is valid */
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args[2] = uint->zero; /* DONE bit */
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args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
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key->vs_epilog.prim_id_param_offset);
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args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
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args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
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VS_EPILOG_PRIMID_LOC); /* X */
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args[6] = uint->undef; /* Y */
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args[7] = uint->undef; /* Z */
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args[8] = uint->undef; /* W */
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lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
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LLVMVoidTypeInContext(base->gallivm->context),
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args, 9, 0);
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}
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/* Compile. */
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LLVMBuildRet(gallivm->builder, ctx.return_value);
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radeon_llvm_finalize_module(&ctx.radeon_bld);
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if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
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gallivm->module, debug, ctx.type,
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"Vertex Shader Epilog"))
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status = false;
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radeon_llvm_dispose(&ctx.radeon_bld);
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return status;
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}
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/**
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* Create & compile a vertex shader epilog. This a helper used by VS and TES.
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*/
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static bool si_get_vs_epilog(struct si_screen *sscreen,
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LLVMTargetMachineRef tm,
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struct si_shader *shader,
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struct pipe_debug_callback *debug,
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struct si_vs_epilog_bits *states)
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{
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union si_shader_part_key epilog_key;
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memset(&epilog_key, 0, sizeof(epilog_key));
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epilog_key.vs_epilog.states = *states;
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/* Set up the PrimitiveID output. */
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if (shader->key.vs.epilog.export_prim_id) {
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unsigned index = shader->selector->info.num_outputs;
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unsigned offset = shader->nr_param_exports++;
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epilog_key.vs_epilog.prim_id_param_offset = offset;
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shader->vs_output_param_offset[index] = offset;
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}
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shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
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&epilog_key, tm, debug,
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si_compile_vs_epilog);
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return shader->epilog != NULL;
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}
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/**
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* Select and compile (or reuse) vertex shader parts (prolog & epilog).
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*/
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static bool si_shader_select_vs_parts(struct si_screen *sscreen,
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LLVMTargetMachineRef tm,
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struct si_shader *shader,
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@ -4889,6 +5018,12 @@ static bool si_shader_select_vs_parts(struct si_screen *sscreen,
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return false;
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}
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/* Get the epilog. */
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if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
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!si_get_vs_epilog(sscreen, tm, shader, debug,
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&shader->key.vs.epilog))
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return false;
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/* Set the instanceID flag. */
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for (i = 0; i < info->num_inputs; i++)
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if (prolog_key.vs_prolog.states.instance_divisors[i])
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@ -4897,6 +5032,22 @@ static bool si_shader_select_vs_parts(struct si_screen *sscreen,
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return true;
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}
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/**
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* Select and compile (or reuse) TES parts (epilog).
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*/
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static bool si_shader_select_tes_parts(struct si_screen *sscreen,
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LLVMTargetMachineRef tm,
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struct si_shader *shader,
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struct pipe_debug_callback *debug)
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{
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if (shader->key.tes.as_es)
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return true;
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/* TES compiled as VS. */
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return si_get_vs_epilog(sscreen, tm, shader, debug,
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&shader->key.tes.epilog);
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}
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int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
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struct si_shader *shader,
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struct pipe_debug_callback *debug)
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@ -4915,6 +5066,10 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
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if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
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return -1;
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break;
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case PIPE_SHADER_TESS_EVAL:
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if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
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return -1;
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break;
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}
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/* Update SGPR and VGPR counts. */
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@ -274,6 +274,10 @@ union si_shader_part_key {
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unsigned num_input_sgprs:5;
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unsigned last_input:4;
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} vs_prolog;
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struct {
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struct si_vs_epilog_bits states;
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unsigned prim_id_param_offset:5;
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} vs_epilog;
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};
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union si_shader_key {
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