freedreno/a6xx: add missing flush/invalidates for blit
Various things we were missing for multiple blits in a single batch. Signed-off-by: Rob Clark <robdclark@chromium.org>
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@ -172,21 +172,14 @@ can_do_blit(const struct pipe_blit_info *info)
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}
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static void
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emit_setup(struct fd_ringbuffer *ring)
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emit_setup(struct fd_batch *batch)
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{
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
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struct fd_ringbuffer *ring = batch->draw;
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, LRZ_FLUSH);
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_RING(ring, 0x0);
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OUT_WFI5(ring);
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OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
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OUT_RING(ring, 0x10000000);
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fd6_event_write(batch, ring, 0x1d, true);
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fd6_event_write(batch, ring, FACENESS_FLUSH, true);
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fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
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fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
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}
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static uint32_t
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@ -677,7 +670,7 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
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mtx_unlock(&ctx->screen->lock);
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emit_setup(batch->draw);
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emit_setup(batch);
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if ((info->src.resource->target == PIPE_BUFFER) &&
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(info->dst.resource->target == PIPE_BUFFER)) {
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@ -694,6 +687,7 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
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fd6_event_write(batch, batch->draw, 0x1d, true);
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fd6_event_write(batch, batch->draw, FACENESS_FLUSH, true);
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fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
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fd6_cache_inv(batch, batch->draw);
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fd_resource(info->dst.resource)->valid = true;
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batch->needs_flush = true;
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@ -146,7 +146,7 @@ fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
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static inline void
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fd6_cache_inv(struct fd_batch *batch, struct fd_ringbuffer *ring)
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{
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fd6_event_write(batch, ring, 0x31, false);
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fd6_event_write(batch, ring, CACHE_INVALIDATE, false);
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}
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static inline void
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