radeonsi/gfx10: set GE_CNTL for tessellation correctly
to match PAL Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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@ -717,13 +717,18 @@ static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
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*/
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*/
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static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
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static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
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{
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{
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union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
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unsigned ge_cntl;
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unsigned ge_cntl;
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if (sctx->ngg) {
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if (sctx->ngg) {
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ge_cntl = si_get_vs_state(sctx)->ge_cntl |
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if (sctx->tes_shader.cso) {
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S_03096C_PACKET_TO_ONE_PA(sctx->ia_multi_vgt_param_key.u.line_stipple_enabled);
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ge_cntl = S_03096C_PRIM_GRP_SIZE(num_patches) |
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S_03096C_VERT_GRP_SIZE(0) |
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S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
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} else {
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ge_cntl = si_get_vs_state(sctx)->ge_cntl;
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}
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} else {
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} else {
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union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
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unsigned primgroup_size;
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unsigned primgroup_size;
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unsigned vertgroup_size;
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unsigned vertgroup_size;
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@ -741,10 +746,11 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
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ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) |
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ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) |
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S_03096C_VERT_GRP_SIZE(vertgroup_size) |
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S_03096C_VERT_GRP_SIZE(vertgroup_size) |
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S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id) |
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S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
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S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled);
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}
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}
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ge_cntl |= S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled);
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if (ge_cntl != sctx->last_multi_vgt_param) {
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if (ge_cntl != sctx->last_multi_vgt_param) {
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radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
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radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
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sctx->last_multi_vgt_param = ge_cntl;
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sctx->last_multi_vgt_param = ge_cntl;
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