radeonsi: set gfx10 registers better in si_emit_initial_compute_regs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
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@ -423,11 +423,13 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
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}
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if (sctx->chip_class >= GFX10) {
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radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
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radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
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radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
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radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
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radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
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radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 5);
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radeon_emit(cs, 0); /* R_00B890_COMPUTE_USER_ACCUM_0 */
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radeon_emit(cs, 0); /* R_00B894_COMPUTE_USER_ACCUM_1 */
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radeon_emit(cs, 0); /* R_00B898_COMPUTE_USER_ACCUM_2 */
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radeon_emit(cs, 0); /* R_00B89C_COMPUTE_USER_ACCUM_3 */
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radeon_emit(cs, 0); /* R_00B8A0_COMPUTE_PGM_RSRC3 */
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radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
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}
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radeon_end();
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