anv: Bounds-check pushed UBOs when robustBufferAccess = true
We also have to add nir_intrinsic_load_push_constant to the list of intrinsics which use push constants in brw_nir_analyze_ubo_ranges because we're moving the loop where we rewrite the intrinsics to after we've analyzed UBO loads. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
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@ -57,6 +57,7 @@ void anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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struct anv_pipeline_bind_map *map);
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void anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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bool robust_buffer_access,
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nir_shader *nir,
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struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map,
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@ -22,18 +22,22 @@
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*/
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#include "anv_nir.h"
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#include "nir_builder.h"
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#include "compiler/brw_nir.h"
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#include "util/mesa-sha1.h"
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void
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anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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bool robust_buffer_access,
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nir_shader *nir,
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struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map,
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void *mem_ctx)
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{
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const struct brw_compiler *compiler = pdevice->compiler;
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memset(map->push_ranges, 0, sizeof(map->push_ranges));
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bool has_const_ubo = false;
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unsigned push_start = UINT_MAX, push_end = 0;
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nir_foreach_function(function, nir) {
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if (!function->impl)
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@ -45,19 +49,46 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_load_push_constant)
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continue;
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_ubo:
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if (nir_src_is_const(intrin->src[0]) &&
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nir_src_is_const(intrin->src[1]))
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has_const_ubo = true;
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break;
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unsigned base = nir_intrinsic_base(intrin);
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unsigned range = nir_intrinsic_range(intrin);
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push_start = MIN2(push_start, base);
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push_end = MAX2(push_end, base + range);
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case nir_intrinsic_load_push_constant: {
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unsigned base = nir_intrinsic_base(intrin);
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unsigned range = nir_intrinsic_range(intrin);
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push_start = MIN2(push_start, base);
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push_end = MAX2(push_end, base + range);
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break;
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}
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default:
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break;
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}
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}
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}
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}
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const bool has_push_intrinsic = push_start <= push_end;
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const bool push_ubo_ranges =
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(pdevice->info.gen >= 8 || pdevice->info.is_haswell) &&
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has_const_ubo && nir->info.stage != MESA_SHADER_COMPUTE;
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if (push_ubo_ranges && robust_buffer_access) {
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/* We can't on-the-fly adjust our push ranges because doing so would
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* mess up the layout in the shader. When robustBufferAccess is
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* enabled, we have to manually bounds check our pushed UBO accesses.
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*/
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const uint32_t ubo_size_start =
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offsetof(struct anv_push_constants, push_ubo_sizes);
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const uint32_t ubo_size_end = ubo_size_start + (4 * sizeof(uint32_t));
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push_start = MIN2(push_start, ubo_size_start);
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push_end = MAX2(push_end, ubo_size_end);
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}
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if (nir->info.stage == MESA_SHADER_COMPUTE) {
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/* For compute shaders, we always have to have the subgroup ID. The
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* back-end compiler will "helpfully" add it for us in the last push
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@ -76,34 +107,10 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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push_start = MIN2(push_start, push_end);
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push_start = align_down_u32(push_start, 32);
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if (has_push_intrinsic) {
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nir_foreach_function(function, nir) {
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if (!function->impl)
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continue;
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_load_push_constant)
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continue;
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intrin->intrinsic = nir_intrinsic_load_uniform;
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nir_intrinsic_set_base(intrin,
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nir_intrinsic_base(intrin) -
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push_start);
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}
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}
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}
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}
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/* For vec4 our push data size needs to be aligned to a vec4 and for
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* scalar, it needs to be aligned to a DWORD.
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*/
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const unsigned align =
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pdevice->compiler->scalar_stage[nir->info.stage] ? 4 : 16;
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const unsigned align = compiler->scalar_stage[nir->info.stage] ? 4 : 16;
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nir->num_uniforms = ALIGN(push_end - push_start, align);
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prog_data->nr_params = nir->num_uniforms / 4;
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prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
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@ -114,10 +121,11 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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.length = DIV_ROUND_UP(push_end - push_start, 32),
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};
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if ((pdevice->info.gen >= 8 || pdevice->info.is_haswell) &&
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nir->info.stage != MESA_SHADER_COMPUTE) {
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brw_nir_analyze_ubo_ranges(pdevice->compiler, nir, NULL,
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prog_data->ubo_ranges);
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/* Mapping from brw_ubo_range to anv_push_range */
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int push_range_idx_map[4] = { -1, -1, -1, -1 };
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if (push_ubo_ranges) {
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brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
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/* We can push at most 64 registers worth of data. The back-end
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* compiler would do this fixup for us but we'd like to calculate
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@ -137,13 +145,19 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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map->push_ranges[n++] = push_constant_range;
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for (int i = 0; i < 4; i++) {
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const struct brw_ubo_range *ubo_range = &prog_data->ubo_ranges[i];
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struct brw_ubo_range *ubo_range = &prog_data->ubo_ranges[i];
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if (ubo_range->length == 0)
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continue;
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if (n >= 4 || (n == 3 && compiler->constant_buffer_0_is_relative)) {
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memset(ubo_range, 0, sizeof(*ubo_range));
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continue;
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}
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const struct anv_pipeline_binding *binding =
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&map->surface_to_descriptor[ubo_range->block];
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push_range_idx_map[i] = n;
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map->push_ranges[n++] = (struct anv_push_range) {
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.set = binding->set,
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.index = binding->index,
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@ -164,6 +178,133 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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map->push_ranges[0] = push_constant_range;
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}
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if (has_push_intrinsic || (push_ubo_ranges && robust_buffer_access)) {
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nir_foreach_function(function, nir) {
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if (!function->impl)
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continue;
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nir_builder b;
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nir_builder_init(&b, function->impl);
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_ubo: {
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if (!robust_buffer_access)
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break;
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if (!nir_src_is_const(intrin->src[0]) ||
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!nir_src_is_const(intrin->src[1]))
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break;
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uint32_t index = nir_src_as_uint(intrin->src[0]);
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uint64_t offset = nir_src_as_uint(intrin->src[1]);
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uint32_t size = intrin->num_components *
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(intrin->dest.ssa.bit_size / 8);
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int ubo_range_idx = -1;
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for (unsigned i = 0; i < 4; i++) {
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if (prog_data->ubo_ranges[i].length > 0 &&
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prog_data->ubo_ranges[i].block == index) {
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ubo_range_idx = i;
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break;
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}
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}
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if (ubo_range_idx < 0)
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break;
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const struct brw_ubo_range *range =
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&prog_data->ubo_ranges[ubo_range_idx];
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const uint32_t range_end =
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(range->start + range->length) * 32;
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if (range_end < offset || offset + size <= range->start)
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break;
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b.cursor = nir_after_instr(&intrin->instr);
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assert(push_range_idx_map[ubo_range_idx] >= 0);
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const uint32_t ubo_size_offset =
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offsetof(struct anv_push_constants, push_ubo_sizes) +
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push_range_idx_map[ubo_range_idx] * sizeof(uint32_t);
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nir_intrinsic_instr *load_size =
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nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_load_uniform);
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load_size->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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nir_intrinsic_set_base(load_size,
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ubo_size_offset - push_start);
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nir_intrinsic_set_range(load_size, 4);
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nir_intrinsic_set_type(load_size, nir_type_uint32);
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load_size->num_components = 1;
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nir_ssa_dest_init(&load_size->instr, &load_size->dest,
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1, 32, NULL);
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nir_builder_instr_insert(&b, &load_size->instr);
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/* Do the size checks per-component. Thanks to scalar block
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* layout, we could end up with a single vector straddling a
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* 32B boundary.
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*
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* We align up to 32B so that we can get better CSE.
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*
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* We check
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*
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* offset + size - 1 < push_ubo_sizes[i]
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*
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* rather than
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*
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* offset + size <= push_ubo_sizes[i]
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*
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* because it properly returns OOB for the case where
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* offset + size == 0.
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*/
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nir_const_value last_byte_const[NIR_MAX_VEC_COMPONENTS];
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for (unsigned c = 0; c < intrin->dest.ssa.num_components; c++) {
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assert(intrin->dest.ssa.bit_size % 8 == 0);
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const unsigned comp_size_B = intrin->dest.ssa.bit_size / 8;
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const uint32_t comp_last_byte =
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align_u32(offset + (c + 1) * comp_size_B,
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ANV_UBO_BOUNDS_CHECK_ALIGNMENT) - 1;
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last_byte_const[c] =
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nir_const_value_for_uint(comp_last_byte, 32);
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}
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nir_ssa_def *last_byte =
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nir_build_imm(&b, intrin->dest.ssa.num_components, 32,
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last_byte_const);
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nir_ssa_def *in_bounds =
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nir_ult(&b, last_byte, &load_size->dest.ssa);
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nir_ssa_def *zero =
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nir_imm_zero(&b, intrin->dest.ssa.num_components,
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intrin->dest.ssa.bit_size);
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nir_ssa_def *value =
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nir_bcsel(&b, in_bounds, &intrin->dest.ssa, zero);
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nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa,
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nir_src_for_ssa(value),
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value->parent_instr);
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break;
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}
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case nir_intrinsic_load_push_constant:
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intrin->intrinsic = nir_intrinsic_load_uniform;
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nir_intrinsic_set_base(intrin,
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nir_intrinsic_base(intrin) -
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push_start);
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break;
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default:
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break;
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}
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}
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}
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}
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}
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/* Now that we're done computing the push constant portion of the
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* bind map, hash it. This lets us quickly determine if the actual
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* mapping has changed and not just a no-op pipeline change.
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@ -693,8 +693,8 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
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nir_lower_non_uniform_texture_access |
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nir_lower_non_uniform_image_access);
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anv_nir_compute_push_layout(pdevice, nir, prog_data,
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&stage->bind_map, mem_ctx);
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anv_nir_compute_push_layout(pdevice, pipeline->device->robust_buffer_access,
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nir, prog_data, &stage->bind_map, mem_ctx);
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stage->nir = nir;
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}
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@ -2476,6 +2476,9 @@ struct anv_push_constants {
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/** Dynamic offsets for dynamic UBOs and SSBOs */
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uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
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/** Pad out to a multiple of 32 bytes */
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uint32_t push_ubo_sizes[4];
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struct {
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/** Base workgroup ID
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*
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@ -2489,9 +2492,6 @@ struct anv_push_constants {
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* uploading the push constants for compute shaders.
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*/
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uint32_t subgroup_id;
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/** Pad out to a multiple of 32 bytes */
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uint32_t pad[4];
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} cs;
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};
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@ -2938,6 +2938,67 @@ get_push_range_address(struct anv_cmd_buffer *cmd_buffer,
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}
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}
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/** Returns the size in bytes of the bound buffer relative to range->start
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*
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* This may be smaller than range->length * 32.
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*/
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static uint32_t
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get_push_range_bound_size(struct anv_cmd_buffer *cmd_buffer,
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gl_shader_stage stage,
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const struct anv_push_range *range)
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{
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assert(stage != MESA_SHADER_COMPUTE);
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const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
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switch (range->set) {
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case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
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struct anv_descriptor_set *set =
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gfx_state->base.descriptors[range->index];
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assert(range->start * 32 < set->desc_mem.alloc_size);
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assert((range->start + range->length) * 32 < set->desc_mem.alloc_size);
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return set->desc_mem.alloc_size - range->start * 32;
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}
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case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS:
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return range->length * 32;
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default: {
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assert(range->set < MAX_SETS);
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struct anv_descriptor_set *set =
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gfx_state->base.descriptors[range->set];
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const struct anv_descriptor *desc =
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&set->descriptors[range->index];
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if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
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if (range->start * 32 > desc->buffer_view->range)
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return 0;
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return desc->buffer_view->range - range->start * 32;
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} else {
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assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
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/* Compute the offset within the buffer */
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struct anv_push_constants *push =
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&cmd_buffer->state.push_constants[stage];
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uint32_t dynamic_offset =
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push->dynamic_offsets[range->dynamic_offset_index];
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uint64_t offset = desc->offset + dynamic_offset;
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/* Clamp to the buffer size */
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offset = MIN2(offset, desc->buffer->size);
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/* Clamp the range to the buffer size */
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uint32_t bound_range = MIN2(desc->range, desc->buffer->size - offset);
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/* Align the range for consistency */
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bound_range = align_u32(bound_range, ANV_UBO_BOUNDS_CHECK_ALIGNMENT);
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if (range->start * 32 > bound_range)
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return 0;
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return bound_range - range->start * 32;
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}
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}
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}
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}
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static void
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cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
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gl_shader_stage stage,
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@ -3099,7 +3160,30 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer,
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if (anv_pipeline_has_stage(pipeline, stage)) {
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const struct anv_pipeline_bind_map *bind_map =
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&pipeline->shaders[stage]->bind_map;
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struct anv_push_constants *push =
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&cmd_buffer->state.push_constants[stage];
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if (cmd_buffer->device->robust_buffer_access) {
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for (unsigned i = 0; i < 4; i++) {
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const struct anv_push_range *range = &bind_map->push_ranges[i];
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if (range->length == 0) {
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push->push_ubo_sizes[i] = 0;
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} else {
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push->push_ubo_sizes[i] =
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get_push_range_bound_size(cmd_buffer, stage, range);
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}
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cmd_buffer->state.push_constants_dirty |=
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mesa_to_vk_shader_stage(stage);
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}
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}
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/* We have to gather buffer addresses as a second step because the
|
||||
* loop above puts data into the push constant area and the call to
|
||||
* get_push_range_address is what locks our push constants and copies
|
||||
* them into the actual GPU buffer. If we did the two loops at the
|
||||
* same time, we'd risk only having some of the sizes in the push
|
||||
* constant buffer when we did the copy.
|
||||
*/
|
||||
for (unsigned i = 0; i < 4; i++) {
|
||||
const struct anv_push_range *range = &bind_map->push_ranges[i];
|
||||
if (range->length == 0)
|
||||
|
|
Loading…
Reference in New Issue