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st/nir: fix atomic lowering for gallium drivers 

i965 and gallium handle the atomic buffer index differently. It was
just by luck that the single piglit test for this was passing.

For gallium we use the atomic binding so that we match the handling
in st_bind_atomics().

On radeonsi this fixes the CTS test:
KHR-GL43.shader_storage_buffer_object.advanced-write-fragment

It also fixes tressfx hair rendering in Tomb Raider.

Reviewed-by: Marek Olšák  <marek.olsak@amd.com>
This commit is contained in:
Timothy Arceri 2018-03-19 22:23:55 +11:00
parent 632d5e97ef
commit dfe2f19855
4 changed files with 14 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/compiler/nir/nir.h
View File

@ -2710,7 +2710,8 @@ typedef struct nir_lower_bitmap_options {
void nir_lower_bitmap(nir_shader *shader, const nir_lower_bitmap_options *options);
bool nir_lower_atomics(nir_shader *shader,
const struct gl_shader_program *shader_program);
const struct gl_shader_program *shader_program,
bool use_binding_as_idx);
bool nir_lower_atomics_to_ssbo(nir_shader *shader, unsigned ssbo_offset);
bool nir_lower_to_source_mods(nir_shader *shader);

15
src/compiler/nir/nir_lower_atomics.c
View File

@ -38,7 +38,7 @@
static bool
lower_instr(nir_intrinsic_instr *instr,
const struct gl_shader_program *shader_program,
nir_shader *shader)
nir_shader *shader, bool use_binding_as_idx)
{
nir_intrinsic_op op;
switch (instr->intrinsic) {
@ -98,9 +98,12 @@ lower_instr(nir_intrinsic_instr *instr,
void *mem_ctx = ralloc_parent(instr);
unsigned uniform_loc = instr->variables[0]->var->data.location;
unsigned idx = use_binding_as_idx ?
instr->variables[0]->var->data.binding :
shader_program->data->UniformStorage[uniform_loc].opaque[shader->info.stage].index;
nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(mem_ctx, op);
nir_intrinsic_set_base(new_instr,
shader_program->data->UniformStorage[uniform_loc].opaque[shader->info.stage].index);
nir_intrinsic_set_base(new_instr, idx);
nir_load_const_instr *offset_const =
nir_load_const_instr_create(mem_ctx, 1, 32);
@ -174,7 +177,8 @@ lower_instr(nir_intrinsic_instr *instr,
bool
nir_lower_atomics(nir_shader *shader,
const struct gl_shader_program *shader_program)
const struct gl_shader_program *shader_program,
bool use_binding_as_idx)
{
bool progress = false;
@ -184,7 +188,8 @@ nir_lower_atomics(nir_shader *shader,
nir_foreach_instr_safe(instr, block) {
if (instr->type == nir_instr_type_intrinsic)
progress |= lower_instr(nir_instr_as_intrinsic(instr),
shader_program, shader);
shader_program, shader,
use_binding_as_idx);
}
}

2
src/mesa/drivers/dri/i965/brw_link.cpp
View File

@ -299,7 +299,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
brw_shader_gather_info(prog->nir, prog);
NIR_PASS_V(prog->nir, nir_lower_samplers, shProg);
NIR_PASS_V(prog->nir, nir_lower_atomics, shProg);
NIR_PASS_V(prog->nir, nir_lower_atomics, shProg, false);
NIR_PASS_V(prog->nir, nir_lower_atomics_to_ssbo,
prog->nir->info.num_abos);

2
src/mesa/state_tracker/st_glsl_to_nir.cpp
View File

@ -414,7 +414,7 @@ st_glsl_to_nir_post_opts(struct st_context *st, struct gl_program *prog,
st_set_prog_affected_state_flags(prog);
NIR_PASS_V(nir, st_nir_lower_builtin);
NIR_PASS_V(nir, nir_lower_atomics, shader_program);
NIR_PASS_V(nir, nir_lower_atomics, shader_program, true);
if (st->ctx->_Shader->Flags & GLSL_DUMP) {
_mesa_log("\n");