i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.
This was spectacularly unsafe. On my system, address 0 happens to be the hardware status page for the render ring, and the first quadword of that happens to contain nothing we ever look at, but I sure didn't look forward to having to debug some day when, for example, the kernel happened to bind the ringbuffer before binding the hwsp.
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8f9e8d79c8
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@ -52,6 +52,22 @@ static void clear_cache( struct intel_context *intel )
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intel->batch.cached_items = NULL;
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}
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void
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intel_batchbuffer_init(struct intel_context *intel)
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{
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intel_batchbuffer_reset(intel);
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if (intel->gen == 6) {
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/* We can't just use brw_state_batch to get a chunk of space for
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* the gen6 workaround because it involves actually writing to
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* the buffer, and the kernel doesn't let us write to the batch.
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*/
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intel->batch.workaround_bo = drm_intel_bo_alloc(intel->bufmgr,
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"gen6 workaround",
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4096, 4096);
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}
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}
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void
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intel_batchbuffer_reset(struct intel_context *intel)
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{
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@ -76,6 +92,7 @@ intel_batchbuffer_free(struct intel_context *intel)
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{
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drm_intel_bo_unreference(intel->batch.last_bo);
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drm_intel_bo_unreference(intel->batch.bo);
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drm_intel_bo_unreference(intel->batch.workaround_bo);
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clear_cache(intel);
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}
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@ -282,7 +299,8 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
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BEGIN_BATCH(4);
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OUT_BATCH(_3DSTATE_PIPE_CONTROL);
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OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
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OUT_BATCH(0); /* write address */
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OUT_RELOC(intel->batch.workaround_bo,
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I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0);
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OUT_BATCH(0); /* write data */
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ADVANCE_BATCH();
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}
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@ -9,6 +9,7 @@
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#define BATCH_RESERVED 16
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void intel_batchbuffer_init(struct intel_context *intel);
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void intel_batchbuffer_reset(struct intel_context *intel);
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void intel_batchbuffer_free(struct intel_context *intel);
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@ -854,7 +854,7 @@ intelInitContext(struct intel_context *intel,
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if (INTEL_DEBUG & DEBUG_BUFMGR)
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dri_bufmgr_set_debug(intel->bufmgr, GL_TRUE);
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intel_batchbuffer_reset(intel);
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intel_batchbuffer_init(intel);
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intel_fbo_init(intel);
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@ -181,7 +181,8 @@ struct intel_context
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drm_intel_bo *bo;
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/** Last BO submitted to the hardware. Used for glFinish(). */
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drm_intel_bo *last_bo;
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/** BO for post-sync nonzero writes for gen6 workaround. */
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drm_intel_bo *workaround_bo;
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struct cached_batch_item *cached_items;
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uint16_t emit, total;
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