diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f3a8d0c4786..5be524e3bac 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4896,12 +4896,10 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
                                (1 << nir_tex_src_bias) | (1 << nir_tex_src_min_lod) |
                                (1 << nir_tex_src_ms_index) |
                                (separate_g16 ? 0 : (1 << nir_tex_src_ddx) | (1 << nir_tex_src_ddy)),
-                  .only_fold_all = true,
                },
                {
                   .sampler_dims = ~BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE),
                   .src_types = (1 << nir_tex_src_ddx) | (1 << nir_tex_src_ddy),
-                  .only_fold_all = true,
                },
             };
             struct nir_fold_16bit_tex_image_options fold_16bit_options = {
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 6ebad48346c..d07b2b123bb 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -5350,7 +5350,6 @@ bool nir_unpack_16bit_varying_slots(nir_shader *nir, nir_variable_mode modes);
 struct nir_fold_tex_srcs_options {
    unsigned sampler_dims;
    unsigned src_types;
-   bool only_fold_all; /* Only fold sources if all of them can be folded. */
 };
 
 struct nir_fold_16bit_tex_image_options {
diff --git a/src/compiler/nir/nir_lower_mediump.c b/src/compiler/nir/nir_lower_mediump.c
index 7a89827cb19..cd6ca19ee01 100644
--- a/src/compiler/nir/nir_lower_mediump.c
+++ b/src/compiler/nir/nir_lower_mediump.c
@@ -707,10 +707,10 @@ fold_16bit_tex_srcs(nir_builder *b, nir_tex_instr *tex,
        * because it's out of bounds and the higher bits don't
        * matter.
        */
-      if (can_fold_16bit_src(src->ssa, src_type, false))
-         fold_srcs |= (1 << i);
-      else if (options->only_fold_all)
+      if (!can_fold_16bit_src(src->ssa, src_type, false))
          return false;
+
+      fold_srcs |= (1 << i);
    }
 
    u_foreach_bit(i, fold_srcs) {
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index c7f5b489713..98d516fd266 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -782,7 +782,6 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
                          (1 << nir_tex_src_ms_index) |
                          (1 << nir_tex_src_ddx) |
                          (1 << nir_tex_src_ddy),
-            .only_fold_all = true,
          };
          struct nir_fold_16bit_tex_image_options fold_16bit_options = {
             .rounding_mode = nir_rounding_mode_rtz,
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 6776bff33f5..a04614aebaa 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -179,12 +179,10 @@ static void si_late_optimize_16bit_samplers(struct si_screen *sscreen, nir_shade
                       (1 << nir_tex_src_bias) | (1 << nir_tex_src_min_lod) |
                       (1 << nir_tex_src_ms_index) |
                       (has_g16 ? 0 : (1 << nir_tex_src_ddx) | (1 << nir_tex_src_ddy)),
-         .only_fold_all = true,
       },
       {
          .sampler_dims = ~BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE),
          .src_types = (1 << nir_tex_src_ddx) | (1 << nir_tex_src_ddy),
-         .only_fold_all = true,
       },
    };
    struct nir_fold_16bit_tex_image_options fold_16bit_options = {