radv: use ac_compute_surface
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Nicolai Hähnle
Dave Airlie
parent
607e61c40e
commit
df30123794
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@ -45,24 +45,9 @@ static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
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if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
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return -EINVAL;
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/* all dimension must be at least 1 ! */
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if (!surf_info->width || !surf_info->height || !surf_info->depth ||
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!surf_info->array_size)
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return -EINVAL;
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if (!surf->blk_w || !surf->blk_h)
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return -EINVAL;
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switch (surf_info->samples) {
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case 1:
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case 2:
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case 4:
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case 8:
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break;
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default:
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return -EINVAL;
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}
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switch (type) {
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case RADEON_SURF_TYPE_1D:
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if (surf_info->height > 1)
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@ -91,393 +76,28 @@ static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
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return 0;
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}
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static int radv_compute_level(ADDR_HANDLE addrlib,
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const struct ac_surf_info *surf_info,
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struct radeon_surf *surf, bool is_stencil,
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unsigned level, unsigned type, bool compressed,
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ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
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ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
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ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
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{
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struct legacy_surf_level *surf_level;
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ADDR_E_RETURNCODE ret;
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AddrSurfInfoIn->mipLevel = level;
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AddrSurfInfoIn->width = u_minify(surf_info->width, level);
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AddrSurfInfoIn->height = u_minify(surf_info->height, level);
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if (type == RADEON_SURF_TYPE_3D)
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AddrSurfInfoIn->numSlices = u_minify(surf_info->depth, level);
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else if (type == RADEON_SURF_TYPE_CUBEMAP)
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AddrSurfInfoIn->numSlices = 6;
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else
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AddrSurfInfoIn->numSlices = surf_info->array_size;
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if (level > 0) {
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/* Set the base level pitch. This is needed for calculation
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* of non-zero levels. */
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if (is_stencil)
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AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
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else
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AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
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/* Convert blocks to pixels for compressed formats. */
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if (compressed)
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AddrSurfInfoIn->basePitch *= surf->blk_w;
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}
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ret = AddrComputeSurfaceInfo(addrlib,
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AddrSurfInfoIn,
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AddrSurfInfoOut);
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if (ret != ADDR_OK)
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return ret;
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surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
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surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
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surf_level->slice_size = AddrSurfInfoOut->sliceSize;
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surf_level->nblk_x = AddrSurfInfoOut->pitch;
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surf_level->nblk_y = AddrSurfInfoOut->height;
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switch (AddrSurfInfoOut->tileMode) {
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case ADDR_TM_LINEAR_ALIGNED:
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surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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break;
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case ADDR_TM_1D_TILED_THIN1:
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surf_level->mode = RADEON_SURF_MODE_1D;
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break;
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case ADDR_TM_2D_TILED_THIN1:
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surf_level->mode = RADEON_SURF_MODE_2D;
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break;
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default:
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assert(0);
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}
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if (is_stencil)
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surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
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else
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surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
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surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
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/* Clear DCC fields at the beginning. */
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surf_level->dcc_offset = 0;
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/* The previous level's flag tells us if we can use DCC for this level. */
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if (AddrSurfInfoIn->flags.dccCompatible &&
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(level == 0 || AddrDccOut->subLvlCompressible)) {
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AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
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AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
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AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
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AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
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AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
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ret = AddrComputeDccInfo(addrlib,
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AddrDccIn,
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AddrDccOut);
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if (ret == ADDR_OK) {
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surf_level->dcc_offset = surf->dcc_size;
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surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
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surf->num_dcc_levels = level + 1;
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surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
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surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
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}
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}
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if (!is_stencil && AddrSurfInfoIn->flags.depth &&
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surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
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ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
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ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
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AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
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AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
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AddrHtileIn.height = AddrSurfInfoOut->height;
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AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
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AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
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AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
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AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
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AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
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AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
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ret = AddrComputeHtileInfo(addrlib,
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&AddrHtileIn,
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&AddrHtileOut);
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if (ret == ADDR_OK) {
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surf->htile_size = AddrHtileOut.htileBytes;
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surf->htile_slice_size = AddrHtileOut.sliceSize;
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surf->htile_alignment = AddrHtileOut.baseAlign;
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}
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}
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return 0;
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}
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static void radv_set_micro_tile_mode(struct radeon_surf *surf,
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struct radeon_info *info)
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{
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uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
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if (info->chip_class >= CIK)
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surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
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else
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surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
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}
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static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
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{
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unsigned index, tileb;
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tileb = 8 * 8 * surf->bpe;
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tileb = MIN2(surf->u.legacy.tile_split, tileb);
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for (index = 0; tileb > 64; index++)
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tileb >>= 1;
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assert(index < 16);
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return index;
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}
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static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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const struct ac_surf_info *surf_info,
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struct radeon_surf *surf)
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{
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struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
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unsigned level, mode, type;
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bool compressed;
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ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
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ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
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ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
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ADDR_TILEINFO AddrTileInfoIn = {0};
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ADDR_TILEINFO AddrTileInfoOut = {0};
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unsigned mode, type;
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int r;
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uint32_t last_level = surf_info->levels - 1;
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r = radv_amdgpu_surface_sanity(surf_info, surf);
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if (r)
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return r;
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AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
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AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
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AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
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AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
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AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
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type = RADEON_SURF_GET(surf->flags, TYPE);
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mode = RADEON_SURF_GET(surf->flags, MODE);
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compressed = surf->blk_w == 4 && surf->blk_h == 4;
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/* MSAA and FMASK require 2D tiling. */
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if (surf_info->samples > 1 ||
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(surf->flags & RADEON_SURF_FMASK))
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mode = RADEON_SURF_MODE_2D;
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struct ac_surf_config config;
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/* DB doesn't support linear layouts. */
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if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
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mode < RADEON_SURF_MODE_1D)
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mode = RADEON_SURF_MODE_1D;
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memcpy(&config.info, surf_info, sizeof(config.info));
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config.is_3d = !!(type == RADEON_SURF_TYPE_3D);
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config.is_cube = !!(type == RADEON_SURF_TYPE_CUBEMAP);
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/* Set the requested tiling mode. */
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switch (mode) {
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case RADEON_SURF_MODE_LINEAR_ALIGNED:
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AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
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break;
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case RADEON_SURF_MODE_1D:
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AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
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break;
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case RADEON_SURF_MODE_2D:
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AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
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break;
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default:
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assert(0);
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}
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/* The format must be set correctly for the allocation of compressed
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* textures to work. In other cases, setting the bpp is sufficient. */
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if (compressed) {
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switch (surf->bpe) {
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case 8:
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AddrSurfInfoIn.format = ADDR_FMT_BC1;
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break;
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case 16:
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AddrSurfInfoIn.format = ADDR_FMT_BC3;
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break;
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default:
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assert(0);
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}
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} else {
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AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
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}
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AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf_info->samples;
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AddrSurfInfoIn.tileIndex = -1;
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/* Set the micro tile type. */
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if (surf->flags & RADEON_SURF_SCANOUT)
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AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
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else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
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AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
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else
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AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
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AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
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AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
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AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
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AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
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AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
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AddrSurfInfoIn.flags.pow2Pad = last_level > 0;
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AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.fmask;
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/* DCC notes:
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* - If we add MSAA support, keep in mind that CB can't decompress 8bpp
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* with samples >= 4.
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* - Mipmapped array textures have low performance (discovered by a closed
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* driver team).
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*/
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AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
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!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
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!compressed && AddrDccIn.numSamples <= 1 &&
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((surf_info->array_size == 1 && surf_info->depth == 1) ||
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last_level == 0);
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AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
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AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
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/* noStencil = 0 can result in a depth part that is incompatible with
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* mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
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* this case, we may end up setting stencil_adjusted).
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*
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* TODO: update addrlib to a newer version, remove this, and
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* use flags.matchStencilTileCfg = 1 as an alternative fix.
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*/
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if (last_level > 0)
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AddrSurfInfoIn.flags.noStencil = 1;
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/* Set preferred macrotile parameters. This is usually required
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* for shared resources. This is for 2D tiling only. */
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if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
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surf->u.legacy.bankw && surf->u.legacy.bankh && surf->u.legacy.mtilea &&
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surf->u.legacy.tile_split) {
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/* If any of these parameters are incorrect, the calculation
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* will fail. */
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AddrTileInfoIn.banks = surf->u.legacy.num_banks;
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AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
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AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
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AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
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AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
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AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
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AddrSurfInfoIn.flags.opt4Space = 0;
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AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
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/* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
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* the tile index, because we are expected to know it if
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* we know the other parameters.
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*
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* This is something that can easily be fixed in Addrlib.
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* For now, just figure it out here.
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* Note that only 2D_TILE_THIN1 is handled here.
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*/
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assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
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assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
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if (ws->info.chip_class == SI) {
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if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
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if (surf->bpe == 2)
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AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
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else
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AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
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} else {
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if (surf->bpe == 1)
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AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
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else if (surf->bpe == 2)
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AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
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else if (surf->bpe == 4)
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AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
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else
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AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
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}
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} else {
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if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
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AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
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else
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AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
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AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
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}
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}
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surf->surf_size = 0;
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surf->num_dcc_levels = 0;
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surf->dcc_size = 0;
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surf->dcc_alignment = 1;
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surf->htile_size = surf->htile_slice_size = 0;
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surf->htile_alignment = 1;
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/* Calculate texture layout information. */
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for (level = 0; level <= last_level; level++) {
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r = radv_compute_level(ws->addrlib, surf_info, surf, false, level, type, compressed,
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&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
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if (r)
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break;
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if (level == 0) {
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surf->surf_alignment = AddrSurfInfoOut.baseAlign;
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surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
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radv_set_micro_tile_mode(surf, &ws->info);
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/* For 2D modes only. */
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if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
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surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
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surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
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surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
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surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
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surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
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surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
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} else {
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surf->u.legacy.macro_tile_index = 0;
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}
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}
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}
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/* Calculate texture layout information for stencil. */
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if (surf->flags & RADEON_SURF_SBUFFER) {
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AddrSurfInfoIn.bpp = 8;
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AddrSurfInfoIn.flags.depth = 0;
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AddrSurfInfoIn.flags.stencil = 1;
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/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
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AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
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|
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for (level = 0; level <= last_level; level++) {
|
||||
r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
|
||||
&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/* DB uses the depth pitch for both stencil and depth. */
|
||||
if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
|
||||
surf->u.legacy.stencil_adjusted = true;
|
||||
|
||||
if (level == 0) {
|
||||
/* For 2D modes only. */
|
||||
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
|
||||
surf->u.legacy.stencil_tile_split =
|
||||
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Recalculate the whole DCC miptree size including disabled levels.
|
||||
* This is what addrlib does, but calling addrlib would be a lot more
|
||||
* complicated.
|
||||
*/
|
||||
#if 0
|
||||
if (surf->dcc_size && last_level > 0) {
|
||||
surf->dcc_size = align64(surf->bo_size >> 8,
|
||||
ws->info.pipe_interleave_bytes *
|
||||
ws->info.num_tile_pipes);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
|
||||
}
|
||||
|
||||
static int radv_amdgpu_winsys_surface_best(struct radeon_winsys *rws,
|
||||
|
|
|
|||
Loading…
Reference in New Issue