freedreno/a6xx: remove unnecessary OVERFLOW_FLAG_REG check
The HW deals with overflow automatically, and presumably does it better (only disabling for pipes that had overflow, and using the visiblity data available before the overflow) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5565>
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@ -140,12 +140,7 @@ struct fd6_control {
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uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
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uint32_t _pad0;
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volatile uint32_t vsc_overflow;
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uint32_t _pad1;
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/* flag set from cmdstream when VSC overflow detected: */
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uint32_t vsc_scratch;
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uint32_t _pad2;
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uint32_t _pad3;
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uint32_t _pad4;
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uint32_t _pad1[5];
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/* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
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struct {
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@ -389,12 +389,6 @@ update_vsc_pipe(struct fd_batch *batch)
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A6XX_VSC_DRAW_STRM_LIMIT(.dword = fd6_ctx->vsc_draw_strm_pitch - 64));
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}
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/* TODO we probably have more than 8 scratch regs.. although the first
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* 8 is what kernel dumps, and it is kinda useful to be able to see
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* the value in kernel traces
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*/
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#define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
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/*
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* If overflow is detected, either 0x1 (VSC_DRAW_STRM overflow) or 0x3
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* (VSC_PRIM_STRM overflow) plus the size of the overflowed buffer is
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@ -403,11 +397,6 @@ update_vsc_pipe(struct fd_batch *batch)
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* encoded as well, this protects against already-submitted but
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* not executed batches from fooling the CPU into increasing the
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* size again unnecessarily).
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*
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* To conditionally use VSC data in draw pass only if there is no
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* overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
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* if no overflow, or 0 in case of overflow. The value is inverted
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* to make the CP_COND_REG_EXEC stuff easier.
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*/
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static void
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emit_vsc_overflow_test(struct fd_batch *batch)
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@ -419,11 +408,6 @@ emit_vsc_overflow_test(struct fd_batch *batch)
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debug_assert((fd6_ctx->vsc_draw_strm_pitch & 0x3) == 0);
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debug_assert((fd6_ctx->vsc_prim_strm_pitch & 0x3) == 0);
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/* Clear vsc_scratch: */
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OUT_PKT7(ring, CP_MEM_WRITE, 3);
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OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch));
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OUT_RING(ring, 0x0);
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/* Check for overflow, write vsc_scratch if detected: */
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for (int i = 0; i < gmem->num_vsc_pipes; i++) {
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OUT_PKT7(ring, CP_COND_WRITE5, 8);
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@ -433,7 +417,7 @@ emit_vsc_overflow_test(struct fd_batch *batch)
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OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
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OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_draw_strm_pitch - 64));
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OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
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OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
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OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
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OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_draw_strm_pitch));
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OUT_PKT7(ring, CP_COND_WRITE5, 8);
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@ -443,60 +427,11 @@ emit_vsc_overflow_test(struct fd_batch *batch)
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OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
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OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_prim_strm_pitch - 64));
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OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
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OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
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OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
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OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_prim_strm_pitch));
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}
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OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
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OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
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OUT_PKT7(ring, CP_MEM_TO_REG, 3);
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OUT_RING(ring, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
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CP_MEM_TO_REG_0_CNT(0));
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OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* SRC_LO/HI */
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/*
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* This is a bit awkward, we really want a way to invert the
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* CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
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* execute cmds to use hwbinning when a bit is *not* set. This
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* dance is to invert OVERFLOW_FLAG_REG
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*
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* A CP_NOP packet is used to skip executing the 'else' clause
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* if (b0 set)..
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*/
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BEGIN_RING(ring, 10); /* ensure if/else doesn't get split */
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/* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
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OUT_PKT7(ring, CP_REG_TEST, 1);
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OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
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A6XX_CP_REG_TEST_0_BIT(0) |
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A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
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OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
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OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
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OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(7));
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/* if (b0 set) */ {
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/*
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* On overflow, mirror the value to control->vsc_overflow
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* which CPU is checking to detect overflow (see
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* check_vsc_overflow())
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*/
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OUT_PKT7(ring, CP_REG_TO_MEM, 3);
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OUT_RING(ring, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
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CP_REG_TO_MEM_0_CNT(1 - 1));
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OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow));
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OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
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OUT_RING(ring, 0x0);
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OUT_PKT7(ring, CP_NOP, 2); /* skip 'else' when 'if' is taken */
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} /* else */ {
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OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
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OUT_RING(ring, 0x1);
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}
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}
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static void
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@ -867,41 +802,18 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
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OUT_PKT7(ring, CP_SET_MODE, 1);
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OUT_RING(ring, 0x0);
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/*
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* Conditionally execute if no VSC overflow:
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*/
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OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
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OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
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CP_SET_BIN_DATA5_0_VSC_N(tile->n));
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OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* per-pipe draw-stream address */
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(tile->p * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
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OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
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(tile->p * 4) + (32 * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
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OUT_RELOC(ring, fd6_ctx->vsc_prim_strm,
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(tile->p * fd6_ctx->vsc_prim_strm_pitch), 0, 0);
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BEGIN_RING(ring, 18); /* ensure if/else doesn't get split */
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OUT_PKT7(ring, CP_REG_TEST, 1);
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OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
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A6XX_CP_REG_TEST_0_BIT(0) |
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A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
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OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
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OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
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OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(11));
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/* if (no overflow) */ {
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OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
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OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
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CP_SET_BIN_DATA5_0_VSC_N(tile->n));
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OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* per-pipe draw-stream address */
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(tile->p * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
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OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
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(tile->p * 4) + (32 * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
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OUT_RELOC(ring, fd6_ctx->vsc_prim_strm,
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(tile->p * fd6_ctx->vsc_prim_strm_pitch), 0, 0);
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OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
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OUT_RING(ring, 0x0);
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/* use a NOP packet to skip over the 'else' side: */
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OUT_PKT7(ring, CP_NOP, 2);
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} /* else */ {
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OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
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OUT_RING(ring, 0x1);
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}
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OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
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OUT_RING(ring, 0x0);
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set_window_offset(ring, x1, y1);
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@ -1329,23 +1241,8 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
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struct fd_ringbuffer *ring = batch->gmem;
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if (use_hw_binning(batch)) {
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/* Conditionally execute if no VSC overflow: */
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BEGIN_RING(ring, 7); /* ensure if/else doesn't get split */
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OUT_PKT7(ring, CP_REG_TEST, 1);
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OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
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A6XX_CP_REG_TEST_0_BIT(0) |
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A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
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OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
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OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
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OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(2));
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/* if (no overflow) */ {
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OUT_PKT7(ring, CP_SET_MARKER, 1);
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OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
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}
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OUT_PKT7(ring, CP_SET_MARKER, 1);
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OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
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}
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OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
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