diff --git a/src/amd/addrlib/inc/addrinterface.h b/src/amd/addrlib/inc/addrinterface.h index bbde582a13e..807098fae1f 100644 --- a/src/amd/addrlib/inc/addrinterface.h +++ b/src/amd/addrlib/inc/addrinterface.h @@ -3394,6 +3394,35 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT }; ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information + + /* The equation for doing DCC address computations in shaders. */ + union { + /* This is chip-specific, and it varies with: + * - resource type + * - swizzle_mode + * - bpp + * - number of fragments + * - pipe_aligned + * - rb_aligned + */ + struct { + UINT_8 num_bits; + + struct { + struct { + UINT_8 dim; /* 0..4 as index, 5 means invalid */ + UINT_8 ord; /* 0..31 */ + } coord[8]; /* 0..num_coords */ + } bit[32]; /* 0..num_bits */ + UINT_8 numPipeBits; + } gfx9; + + /* This is chip-specific, it requires 64KB_R_X, and it varies with: + * - bpp + * - pipe_aligned + */ + UINT_16 *gfx10_bits; /* 68 2-byte elements */ + } equation; } ADDR2_COMPUTE_DCCINFO_OUTPUT; /** diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp index 0ffee23467c..4ded4c3b50a 100644 --- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp +++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp @@ -496,6 +496,53 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeDccInfo( pOut->pMipInfo[0].sliceSize = pOut->dccRamSliceSize; } } + + // Get the DCC address equation (copied from DccAddrFromCoord) + const UINT_32 elemLog2 = Log2(pIn->bpp >> 3); + const UINT_32 numPipeLog2 = m_pipesLog2; + UINT_32 index = m_dccBaseIndex + elemLog2; + const UINT_8* patIdxTable; + + if (m_settings.supportRbPlus) + { + patIdxTable = GFX10_DCC_64K_R_X_RBPLUS_PATIDX; + + if (pIn->dccKeyFlags.pipeAligned) + { + index += MaxNumOfBpp; + + if (m_numPkrLog2 < 2) + { + index += m_pipesLog2 * MaxNumOfBpp; + } + else + { + // 4 groups for "m_numPkrLog2 < 2" case + index += 4 * MaxNumOfBpp; + + const UINT_32 dccPipePerPkr = 3; + + index += (m_numPkrLog2 - 2) * dccPipePerPkr * MaxNumOfBpp + + (m_pipesLog2 - m_numPkrLog2) * MaxNumOfBpp; + } + } + } + else + { + patIdxTable = GFX10_DCC_64K_R_X_PATIDX; + + if (pIn->dccKeyFlags.pipeAligned) + { + index += (numPipeLog2 + UnalignedDccType) * MaxNumOfBpp; + } + else + { + index += Min(numPipeLog2, UnalignedDccType - 1) * MaxNumOfBpp; + } + } + + ADDR_C_ASSERT(sizeof(GFX10_DCC_64K_R_X_SW_PATTERN[patIdxTable[index]]) == 68 * 2); + pOut->equation.gfx10_bits = (UINT_16*)GFX10_DCC_64K_R_X_SW_PATTERN[patIdxTable[index]]; } } @@ -2279,7 +2326,7 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeNonBlockCompressedView( // For any mipmap level, move nonBc view base address by offset HwlComputeSubResourceOffsetForSwizzlePattern(&subOffIn, &subOffOut); - pOut->offset = subOffOut.offset; + pOut->offset = subOffOut.offset; ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT slicePbXorIn = {}; slicePbXorIn.bpe = infoIn.bpp; diff --git a/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp index 59a4c86129e..74616507915 100644 --- a/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp +++ b/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp @@ -665,6 +665,55 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeDccInfo( pOut->metaBlkNumPerSlice = numMetaBlkX * numMetaBlkY; pOut->fastClearSizePerSlice = pOut->metaBlkNumPerSlice * numCompressBlkPerMetaBlk * Min(numFrags, m_maxCompFrag); + + // Get the DCC address equation (copied from DccAddrFromCoord) + UINT_32 elementBytesLog2 = Log2(pIn->bpp >> 3); + UINT_32 numSamplesLog2 = Log2(pIn->numFrags); + UINT_32 metaBlkWidthLog2 = Log2(pOut->metaBlkWidth); + UINT_32 metaBlkHeightLog2 = Log2(pOut->metaBlkHeight); + UINT_32 metaBlkDepthLog2 = Log2(pOut->metaBlkDepth); + UINT_32 compBlkWidthLog2 = Log2(pOut->compressBlkWidth); + UINT_32 compBlkHeightLog2 = Log2(pOut->compressBlkHeight); + UINT_32 compBlkDepthLog2 = Log2(pOut->compressBlkDepth); + + MetaEqParams metaEqParams = {0, elementBytesLog2, numSamplesLog2, pIn->dccKeyFlags, + Gfx9DataColor, pIn->swizzleMode, pIn->resourceType, + metaBlkWidthLog2, metaBlkHeightLog2, metaBlkDepthLog2, + compBlkWidthLog2, compBlkHeightLog2, compBlkDepthLog2}; + + CoordEq *eq = (CoordEq *)((Gfx9Lib *)this)->GetMetaEquation(metaEqParams); + + // Generate the DCC address equation. + pOut->equation.gfx9.num_bits = Min(32u, eq->getsize()); + bool checked = false; + for (unsigned b = 0; b < pOut->equation.gfx9.num_bits; b++) { + CoordTerm &bit = (*eq)[b]; + + unsigned c; + for (c = 0; c < bit.getsize(); c++) { + Coordinate &coord = bit[c]; + pOut->equation.gfx9.bit[b].coord[c].dim = coord.getdim(); + pOut->equation.gfx9.bit[b].coord[c].ord = coord.getord(); + } + for (; c < 5; c++) + pOut->equation.gfx9.bit[b].coord[c].dim = 5; /* meaning invalid */ + } + + // Reduce num_bits because DIM_M fills the rest of the bits monotonically. + for (int b = pOut->equation.gfx9.num_bits - 1; b >= 1; b--) { + CoordTerm &prev = (*eq)[b - 1]; + CoordTerm &cur = (*eq)[b]; + + if (cur.getsize() == 1 && cur[0].getdim() == DIM_M && + prev.getsize() == 1 && prev[0].getdim() == DIM_M && + prev[0].getord() + 1 == cur[0].getord()) + pOut->equation.gfx9.num_bits = b; + else + break; + } + + pOut->equation.gfx9.numPipeBits = GetPipeLog2ForMetaAddressing(pIn->dccKeyFlags.pipeAligned, + pIn->swizzleMode); } return ADDR_OK;