radeonsi/nir: call some more var optimisation passes
shader-db results (VEGA64): Totals from affected shaders: SGPRS: 5328912 -> 5329680 (0.01 %) VGPRS: 2969308 -> 2969164 (-0.00 %) Spilled SGPRs: 37921 -> 37917 (-0.01 %) Spilled VGPRs: 32882 -> 29024 (-11.73 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 1400 -> 1200 (-14.29 %) dwords per thread Code Size: 121126000 -> 121282784 (0.13 %) bytes LDS: 1501 -> 1501 (0.00 %) blocks Max Waves: 933188 -> 933229 (0.00 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -841,9 +841,6 @@ si_lower_nir(struct si_shader_selector* sel)
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* - ensure constant offsets for texture instructions are folded
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* and copy-propagated
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*/
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NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
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NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
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NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
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static const struct nir_lower_tex_options lower_tex_options = {
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.lower_txp = ~0u,
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@ -866,6 +863,14 @@ si_lower_nir(struct si_shader_selector* sel)
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do {
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progress = false;
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NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
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NIR_PASS(progress, sel->nir, nir_opt_copy_prop_vars);
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NIR_PASS(progress, sel->nir, nir_opt_dead_write_vars);
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NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
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NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
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/* (Constant) copy propagation is needed for txf with offsets. */
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NIR_PASS(progress, sel->nir, nir_copy_prop);
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NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
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