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radv/winsys: spoof some values for num_render_backends in the null winsys 

To avoid crashes when RADV_FORCE_FAMILY is set to GFX9+ because
num_render_backends is used to compute binning state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
This commit is contained in:
Samuel Pitoiset 2020-03-06 10:23:41 +01:00
parent b911af06cd
commit de550805c5
1 changed files with 32 additions and 40 deletions
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72
src/amd/vulkan/winsys/null/radv_null_winsys.c
View File

@ -31,50 +31,41 @@
#include "ac_llvm_util.h"
/* Hardcode some PCI IDs to allow external tools to recognize chips. */
/* Hardcode some GPU info that are needed for the driver or for some tools. */
static const struct {
enum radeon_family family;
uint32_t pci_id;
} pci_ids[] = {
{ CHIP_TAHITI, 0x6780 },
{ CHIP_PITCAIRN, 0x6800 },
{ CHIP_VERDE, 0x6820 },
{ CHIP_OLAND, 0x6060 },
{ CHIP_HAINAN, 0x6660 },
{ CHIP_BONAIRE, 0x6640 },
{ CHIP_KAVERI, 0x1304 },
{ CHIP_KABINI, 0x9830 },
{ CHIP_HAWAII, 0x67A0 },
{ CHIP_TONGA, 0x6920 },
{ CHIP_ICELAND, 0x6900 },
{ CHIP_CARRIZO, 0x9870 },
{ CHIP_FIJI, 0x7300 },
{ CHIP_STONEY, 0x98E4 },
{ CHIP_POLARIS10, 0x67C0 },
{ CHIP_POLARIS11, 0x67E0 },
{ CHIP_POLARIS12, 0x6980 },
{ CHIP_VEGAM, 0x694C },
{ CHIP_VEGA10, 0x6860 },
{ CHIP_VEGA12, 0x69A0 },
{ CHIP_VEGA20, 0x66A0 },
{ CHIP_RAVEN, 0x15DD },
{ CHIP_RENOIR, 0x1636 },
{ CHIP_ARCTURUS, 0x738C },
{ CHIP_NAVI10, 0x7310 },
{ CHIP_NAVI12, 0x7360 },
{ CHIP_NAVI14, 0x7340 },
uint32_t num_render_backends;
} gpu_info[] = {
{ CHIP_TAHITI, 0x6780, 8 },
{ CHIP_PITCAIRN, 0x6800, 8, },
{ CHIP_VERDE, 0x6820, 4 },
{ CHIP_OLAND, 0x6060, 2 },
{ CHIP_HAINAN, 0x6660, 2 },
{ CHIP_BONAIRE, 0x6640, 4 },
{ CHIP_KAVERI, 0x1304, 2 },
{ CHIP_KABINI, 0x9830, 2 },
{ CHIP_HAWAII, 0x67A0, 16 },
{ CHIP_TONGA, 0x6920, 8 },
{ CHIP_ICELAND, 0x6900, 2 },
{ CHIP_CARRIZO, 0x9870, 2 },
{ CHIP_FIJI, 0x7300, 16 },
{ CHIP_STONEY, 0x98E4, 2 },
{ CHIP_POLARIS10, 0x67C0, 8 },
{ CHIP_POLARIS11, 0x67E0, 4 },
{ CHIP_POLARIS12, 0x6980, 4 },
{ CHIP_VEGAM, 0x694C, 4 },
{ CHIP_VEGA10, 0x6860, 16 },
{ CHIP_VEGA12, 0x69A0, 8 },
{ CHIP_VEGA20, 0x66A0, 16 },
{ CHIP_RAVEN, 0x15DD, 2 },
{ CHIP_RENOIR, 0x1636, 2 },
{ CHIP_ARCTURUS, 0x738C, 2 },
{ CHIP_NAVI10, 0x7310, 16 },
{ CHIP_NAVI12, 0x7360, 8 },
{ CHIP_NAVI14, 0x7340, 8 },
};
static uint32_t
radv_null_winsys_get_pci_id(enum radeon_family family)
{
for (unsigned i = 0; i < ARRAY_SIZE(pci_ids); i++) {
if (pci_ids[i].family == family)
return pci_ids[i].pci_id;
}
return 0;
}
static void radv_null_winsys_query_info(struct radeon_winsys *rws,
struct radeon_info *info)
{
@ -108,7 +99,7 @@ static void radv_null_winsys_query_info(struct radeon_winsys *rws,
abort();
}
info->pci_id = radv_null_winsys_get_pci_id(info->family);
info->pci_id = gpu_info[info->family].pci_id;
info->has_syncobj_wait_for_submit = true;
info->max_se = 4;
info->max_wave64_per_simd = info->family >= CHIP_POLARIS10 &&
@ -124,6 +115,7 @@ static void radv_null_winsys_query_info(struct radeon_winsys *rws,
info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
info->num_render_backends = gpu_info[info->family].num_render_backends;
}
static void radv_null_winsys_destroy(struct radeon_winsys *rws)