i965/vs: Move some functions from brw_vec4_emit.cpp to brw_vec4.cpp.
This leaves only the final code generation stage in brw_vec4_emit.cpp, moving the payload setup, run(), and brw_vs_emit functions to brw_vec4.cpp. The fragment shader backend puts these functions in brw_fs.cpp, so this patch also helps with consistency. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Kenneth Graunke
parent
9947470655
commit
dd50c88386
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@ -22,13 +22,18 @@
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*/
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#include "brw_vec4.h"
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#include "glsl/ir_print_visitor.h"
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extern "C" {
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#include "main/macros.h"
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#include "program/prog_print.h"
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#include "program/prog_parameter.h"
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}
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#define MAX_INSTRUCTION (1 << 30)
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using namespace brw;
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namespace brw {
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/**
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@ -913,4 +918,264 @@ vec4_visitor::dump_instructions()
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}
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}
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int
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vec4_visitor::setup_attributes(int payload_reg)
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{
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int nr_attributes;
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int attribute_map[VERT_ATTRIB_MAX + 1];
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nr_attributes = 0;
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for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
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if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
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attribute_map[i] = payload_reg + nr_attributes;
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nr_attributes++;
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}
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}
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/* VertexID is stored by the VF as the last vertex element, but we
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* don't represent it with a flag in inputs_read, so we call it
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* VERT_ATTRIB_MAX.
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*/
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if (prog_data->uses_vertexid) {
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attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
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nr_attributes++;
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}
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foreach_list(node, &this->instructions) {
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vec4_instruction *inst = (vec4_instruction *)node;
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/* We have to support ATTR as a destination for GL_FIXED fixup. */
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if (inst->dst.file == ATTR) {
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int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
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struct brw_reg reg = brw_vec8_grf(grf, 0);
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reg.type = inst->dst.type;
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reg.dw1.bits.writemask = inst->dst.writemask;
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inst->dst.file = HW_REG;
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inst->dst.fixed_hw_reg = reg;
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}
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].file != ATTR)
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continue;
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int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
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struct brw_reg reg = brw_vec8_grf(grf, 0);
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reg.dw1.bits.swizzle = inst->src[i].swizzle;
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reg.type = inst->src[i].type;
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if (inst->src[i].abs)
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reg = brw_abs(reg);
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if (inst->src[i].negate)
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reg = negate(reg);
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inst->src[i].file = HW_REG;
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inst->src[i].fixed_hw_reg = reg;
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}
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}
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/* The BSpec says we always have to read at least one thing from
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* the VF, and it appears that the hardware wedges otherwise.
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*/
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if (nr_attributes == 0)
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nr_attributes = 1;
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prog_data->urb_read_length = (nr_attributes + 1) / 2;
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unsigned vue_entries = MAX2(nr_attributes, c->prog_data.vue_map.num_slots);
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if (intel->gen == 6)
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c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8;
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else
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c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4;
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return payload_reg + nr_attributes;
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}
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int
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vec4_visitor::setup_uniforms(int reg)
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{
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/* The pre-gen6 VS requires that some push constants get loaded no
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* matter what, or the GPU would hang.
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*/
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if (intel->gen < 6 && this->uniforms == 0) {
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this->uniform_vector_size[this->uniforms] = 1;
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for (unsigned int i = 0; i < 4; i++) {
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unsigned int slot = this->uniforms * 4 + i;
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static float zero = 0.0;
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c->prog_data.param[slot] = &zero;
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}
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this->uniforms++;
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reg++;
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} else {
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reg += ALIGN(uniforms, 2) / 2;
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}
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c->prog_data.nr_params = this->uniforms * 4;
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c->prog_data.curb_read_length = reg - 1;
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return reg;
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}
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void
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vec4_visitor::setup_payload(void)
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{
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int reg = 0;
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/* The payload always contains important data in g0, which contains
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* the URB handles that are passed on to the URB write at the end
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* of the thread. So, we always start push constants at g1.
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*/
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reg++;
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reg = setup_uniforms(reg);
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reg = setup_attributes(reg);
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this->first_non_payload_grf = reg;
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}
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bool
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vec4_visitor::run()
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{
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emit_attribute_fixups();
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/* Generate VS IR for main(). (the visitor only descends into
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* functions called "main").
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*/
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if (shader) {
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visit_instructions(shader->ir);
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} else {
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emit_vertex_program_code();
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}
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if (c->key.userclip_active && !c->key.uses_clip_distance)
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setup_uniform_clipplane_values();
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emit_urb_writes();
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/* Before any optimization, push array accesses out to scratch
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* space where we need them to be. This pass may allocate new
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* virtual GRFs, so we want to do it early. It also makes sure
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* that we have reladdr computations available for CSE, since we'll
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* often do repeated subexpressions for those.
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*/
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if (shader) {
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move_grf_array_access_to_scratch();
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move_uniform_array_access_to_pull_constants();
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} else {
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/* The ARB_vertex_program frontend emits pull constant loads directly
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* rather than using reladdr, so we don't need to walk through all the
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* instructions looking for things to move. There isn't anything.
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*
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* We do still need to split things to vec4 size.
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*/
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split_uniform_registers();
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}
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pack_uniform_registers();
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move_push_constants_to_pull_constants();
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split_virtual_grfs();
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bool progress;
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do {
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progress = false;
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progress = dead_code_eliminate() || progress;
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progress = opt_copy_propagation() || progress;
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progress = opt_algebraic() || progress;
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progress = opt_compute_to_mrf() || progress;
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} while (progress);
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if (failed)
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return false;
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setup_payload();
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if (false) {
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/* Debug of register spilling: Go spill everything. */
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const int grf_count = virtual_grf_count;
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float spill_costs[virtual_grf_count];
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bool no_spill[virtual_grf_count];
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evaluate_spill_costs(spill_costs, no_spill);
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for (int i = 0; i < grf_count; i++) {
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if (no_spill[i])
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continue;
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spill_reg(i);
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}
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}
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while (!reg_allocate()) {
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if (failed)
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break;
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}
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if (failed)
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return false;
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brw_set_access_mode(p, BRW_ALIGN_16);
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generate_code();
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return !failed;
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}
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} /* namespace brw */
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extern "C" {
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bool
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brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
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{
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struct brw_context *brw = c->func.brw;
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struct intel_context *intel = &c->func.brw->intel;
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bool start_busy = false;
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float start_time = 0;
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if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
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start_busy = (intel->batch.last_bo &&
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drm_intel_bo_busy(intel->batch.last_bo));
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start_time = get_time();
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}
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struct brw_shader *shader = NULL;
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if (prog)
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shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
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if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
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if (shader) {
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printf("GLSL IR for native vertex shader %d:\n", prog->Name);
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_mesa_print_ir(shader->ir, NULL);
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printf("\n\n");
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} else {
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printf("ARB_vertex_program %d for native vertex shader\n",
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c->vp->program.Base.Id);
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_mesa_print_program(&c->vp->program.Base);
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}
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}
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if (unlikely(INTEL_DEBUG & DEBUG_PERF) && shader) {
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if (shader->compiled_once) {
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brw_vs_debug_recompile(brw, prog, &c->key);
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}
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if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
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perf_debug("VS compile took %.03f ms and stalled the GPU\n",
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(get_time() - start_time) * 1000);
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}
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shader->compiled_once = true;
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}
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vec4_visitor v(c, prog, shader);
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if (!v.run()) {
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prog->LinkStatus = false;
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ralloc_strcat(&prog->InfoLog, v.fail_msg);
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return false;
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}
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return true;
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}
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} /* extern "C" */
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@ -21,7 +21,6 @@
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*/
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#include "brw_vec4.h"
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#include "glsl/ir_print_visitor.h"
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extern "C" {
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#include "brw_eu.h"
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@ -30,131 +29,8 @@ extern "C" {
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#include "program/prog_parameter.h"
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};
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using namespace brw;
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namespace brw {
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int
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vec4_visitor::setup_attributes(int payload_reg)
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{
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int nr_attributes;
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int attribute_map[VERT_ATTRIB_MAX + 1];
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nr_attributes = 0;
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for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
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if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
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attribute_map[i] = payload_reg + nr_attributes;
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nr_attributes++;
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}
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}
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/* VertexID is stored by the VF as the last vertex element, but we
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* don't represent it with a flag in inputs_read, so we call it
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* VERT_ATTRIB_MAX.
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*/
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if (prog_data->uses_vertexid) {
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attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
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nr_attributes++;
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}
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foreach_list(node, &this->instructions) {
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vec4_instruction *inst = (vec4_instruction *)node;
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/* We have to support ATTR as a destination for GL_FIXED fixup. */
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if (inst->dst.file == ATTR) {
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int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
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struct brw_reg reg = brw_vec8_grf(grf, 0);
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reg.type = inst->dst.type;
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reg.dw1.bits.writemask = inst->dst.writemask;
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inst->dst.file = HW_REG;
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inst->dst.fixed_hw_reg = reg;
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}
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].file != ATTR)
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continue;
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int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
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struct brw_reg reg = brw_vec8_grf(grf, 0);
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reg.dw1.bits.swizzle = inst->src[i].swizzle;
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reg.type = inst->src[i].type;
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if (inst->src[i].abs)
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reg = brw_abs(reg);
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if (inst->src[i].negate)
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reg = negate(reg);
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inst->src[i].file = HW_REG;
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inst->src[i].fixed_hw_reg = reg;
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}
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}
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/* The BSpec says we always have to read at least one thing from
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* the VF, and it appears that the hardware wedges otherwise.
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*/
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if (nr_attributes == 0)
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nr_attributes = 1;
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prog_data->urb_read_length = (nr_attributes + 1) / 2;
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unsigned vue_entries = MAX2(nr_attributes, c->prog_data.vue_map.num_slots);
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if (intel->gen == 6)
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c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8;
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else
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c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4;
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return payload_reg + nr_attributes;
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}
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int
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vec4_visitor::setup_uniforms(int reg)
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{
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/* The pre-gen6 VS requires that some push constants get loaded no
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* matter what, or the GPU would hang.
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*/
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if (intel->gen < 6 && this->uniforms == 0) {
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this->uniform_vector_size[this->uniforms] = 1;
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for (unsigned int i = 0; i < 4; i++) {
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unsigned int slot = this->uniforms * 4 + i;
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static float zero = 0.0;
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c->prog_data.param[slot] = &zero;
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}
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this->uniforms++;
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reg++;
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} else {
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reg += ALIGN(uniforms, 2) / 2;
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}
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c->prog_data.nr_params = this->uniforms * 4;
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c->prog_data.curb_read_length = reg - 1;
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return reg;
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}
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void
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vec4_visitor::setup_payload(void)
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{
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int reg = 0;
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/* The payload always contains important data in g0, which contains
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* the URB handles that are passed on to the URB write at the end
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* of the thread. So, we always start push constants at g1.
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*/
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reg++;
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reg = setup_uniforms(reg);
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reg = setup_attributes(reg);
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this->first_non_payload_grf = reg;
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}
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struct brw_reg
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vec4_instruction::get_dst(void)
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{
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@ -773,90 +649,6 @@ vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
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}
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}
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bool
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vec4_visitor::run()
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{
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emit_attribute_fixups();
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/* Generate VS IR for main(). (the visitor only descends into
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* functions called "main").
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*/
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if (shader) {
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visit_instructions(shader->ir);
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} else {
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emit_vertex_program_code();
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}
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if (c->key.userclip_active && !c->key.uses_clip_distance)
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setup_uniform_clipplane_values();
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emit_urb_writes();
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|
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/* Before any optimization, push array accesses out to scratch
|
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* space where we need them to be. This pass may allocate new
|
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* virtual GRFs, so we want to do it early. It also makes sure
|
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* that we have reladdr computations available for CSE, since we'll
|
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* often do repeated subexpressions for those.
|
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*/
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if (shader) {
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move_grf_array_access_to_scratch();
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move_uniform_array_access_to_pull_constants();
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} else {
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/* The ARB_vertex_program frontend emits pull constant loads directly
|
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* rather than using reladdr, so we don't need to walk through all the
|
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* instructions looking for things to move. There isn't anything.
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*
|
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* We do still need to split things to vec4 size.
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*/
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split_uniform_registers();
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}
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pack_uniform_registers();
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move_push_constants_to_pull_constants();
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split_virtual_grfs();
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bool progress;
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do {
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progress = false;
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progress = dead_code_eliminate() || progress;
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progress = opt_copy_propagation() || progress;
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progress = opt_algebraic() || progress;
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progress = opt_compute_to_mrf() || progress;
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} while (progress);
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if (failed)
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return false;
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setup_payload();
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if (false) {
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/* Debug of register spilling: Go spill everything. */
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const int grf_count = virtual_grf_count;
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float spill_costs[virtual_grf_count];
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bool no_spill[virtual_grf_count];
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evaluate_spill_costs(spill_costs, no_spill);
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for (int i = 0; i < grf_count; i++) {
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if (no_spill[i])
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continue;
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spill_reg(i);
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}
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}
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while (!reg_allocate()) {
|
||||
if (failed)
|
||||
break;
|
||||
}
|
||||
|
||||
if (failed)
|
||||
return false;
|
||||
|
||||
brw_set_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
generate_code();
|
||||
|
||||
return !failed;
|
||||
}
|
||||
|
||||
void
|
||||
vec4_visitor::generate_code()
|
||||
{
|
||||
|
|
@ -1052,59 +844,4 @@ vec4_visitor::generate_code()
|
|||
}
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
|
||||
bool
|
||||
brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
|
||||
{
|
||||
struct brw_context *brw = c->func.brw;
|
||||
struct intel_context *intel = &c->func.brw->intel;
|
||||
bool start_busy = false;
|
||||
float start_time = 0;
|
||||
|
||||
if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
|
||||
start_busy = (intel->batch.last_bo &&
|
||||
drm_intel_bo_busy(intel->batch.last_bo));
|
||||
start_time = get_time();
|
||||
}
|
||||
|
||||
struct brw_shader *shader = NULL;
|
||||
if (prog)
|
||||
shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
|
||||
|
||||
if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
|
||||
if (shader) {
|
||||
printf("GLSL IR for native vertex shader %d:\n", prog->Name);
|
||||
_mesa_print_ir(shader->ir, NULL);
|
||||
printf("\n\n");
|
||||
} else {
|
||||
printf("ARB_vertex_program %d for native vertex shader\n",
|
||||
c->vp->program.Base.Id);
|
||||
_mesa_print_program(&c->vp->program.Base);
|
||||
}
|
||||
}
|
||||
|
||||
if (unlikely(INTEL_DEBUG & DEBUG_PERF) && shader) {
|
||||
if (shader->compiled_once) {
|
||||
brw_vs_debug_recompile(brw, prog, &c->key);
|
||||
}
|
||||
if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
|
||||
perf_debug("VS compile took %.03f ms and stalled the GPU\n",
|
||||
(get_time() - start_time) * 1000);
|
||||
}
|
||||
shader->compiled_once = true;
|
||||
}
|
||||
|
||||
vec4_visitor v(c, prog, shader);
|
||||
if (!v.run()) {
|
||||
prog->LinkStatus = false;
|
||||
ralloc_strcat(&prog->InfoLog, v.fail_msg);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
} /* extern "C" */
|
||||
|
||||
} /* namespace brw */
|
||||
|
|
|
|||
Loading…
Reference in New Issue