etnaviv: use nir_lower_uniforms_to_ubo(..)
This removes our local copy and fixes the following nir validation problem: error: nir_intrinsic_range(instr) != 0 (../src/compiler/nir/nir_validate.c:646) No piglit or deqp regression seen. shader-db results for GC3000: instructions helped: shaders/deqp_gles2/23470.shader_test VERT: 328 -> 316 (-3.66%) instructions helped: shaders/deqp_gles2/23473.shader_test FRAG: 328 -> 316 (-3.66%) instructions helped: shaders/glamor/88.shader_test FRAG: 472 -> 452 (-4.24%) instructions helped: shaders/chromeos/36.shader_test VERT: 60 -> 56 (-6.67%) instructions helped: shaders/chromeos/24.shader_test VERT: 60 -> 56 (-6.67%) instructions helped: shaders/chromeos/18.shader_test VERT: 60 -> 56 (-6.67%) instructions helped: shaders/chromeos/45.shader_test VERT: 60 -> 56 (-6.67%) instructions helped: shaders/deqp_gles2/23494.shader_test VERT: 176 -> 164 (-6.82%) instructions helped: shaders/deqp_gles2/23497.shader_test FRAG: 176 -> 164 (-6.82%) instructions helped: shaders/glamor/82.shader_test FRAG: 280 -> 260 (-7.14%) instructions helped: shaders/chromeos/21.shader_test VERT: 56 -> 52 (-7.14%) instructions helped: shaders/chromeos/15.shader_test VERT: 56 -> 52 (-7.14%) instructions helped: shaders/tesseract/268.shader_test VERT: 152 -> 136 (-10.53%) instructions helped: shaders/tesseract/270.shader_test VERT: 184 -> 164 (-10.87%) instructions helped: shaders/tesseract/272.shader_test VERT: 216 -> 192 (-11.11%) instructions helped: shaders/tesseract/266.shader_test VERT: 88 -> 76 (-13.64%) instructions helped: shaders/deqp_gles2/23488.shader_test VERT: 112 -> 96 (-14.29%) instructions helped: shaders/deqp_gles2/23491.shader_test FRAG: 112 -> 96 (-14.29%) instructions helped: shaders/chromeos/102.shader_test VERT: 168 -> 144 (-14.29%) instructions helped: shaders/deqp_gles2/23449.shader_test FRAG: 64 -> 52 (-18.75%) instructions helped: shaders/deqp_gles2/23446.shader_test VERT: 64 -> 52 (-18.75%) instructions helped: shaders/deqp_gles2/23461.shader_test FRAG: 124 -> 100 (-19.35%) instructions helped: shaders/deqp_gles2/23458.shader_test VERT: 124 -> 100 (-19.35%) instructions helped: shaders/chromeos/39.shader_test VERT: 124 -> 100 (-19.35%) temps helped: shaders/chromeos/102.shader_test VERT: 6 -> 5 (-16.67%) temps helped: shaders/deqp_gles2/23470.shader_test VERT: 5 -> 4 (-20.00%) temps helped: shaders/deqp_gles2/23473.shader_test FRAG: 5 -> 4 (-20.00%) temps HURT: shaders/tesseract/272.shader_test VERT: 6 -> 7 (16.67%) immediates helped: shaders/deqp_gles2/23470.shader_test VERT: 24 -> 20 (-16.67%) immediates helped: shaders/deqp_gles2/23473.shader_test FRAG: 24 -> 20 (-16.67%) immediates helped: shaders/chromeos/102.shader_test VERT: 8 -> 4 (-50.00%) immediates helped: shaders/chromeos/39.shader_test VERT: 8 -> 4 (-50.00%) immediates HURT: shaders/glamor/88.shader_test FRAG: 32 -> 36 (12.50%) immediates HURT: shaders/deqp_gles2/23494.shader_test VERT: 4 -> 8 (100.00%) immediates HURT: shaders/deqp_gles2/23497.shader_test FRAG: 4 -> 8 (100.00%) total instructions in shared programs: 1123728 -> 1123392 (-0.03%) instructions in affected programs: 3644 -> 3308 (-9.22%) helped: 24 HURT: 0 helped stats (abs) min: 4 max: 24 x̄: 14.00 x̃: 12 helped stats (rel) min: 3.66% max: 19.35% x̄: 10.74% x̃: 8.83% 95% mean confidence interval for instructions value: -17.11 -10.89 95% mean confidence interval for instructions %-change: -13.03% -8.45% Instructions are helped. total temps in shared programs: 86978 -> 86976 (<.01%) temps in affected programs: 22 -> 20 (-9.09%) helped: 3 HURT: 1 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 16.67% max: 20.00% x̄: 18.89% x̃: 20.00% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 16.67% max: 16.67% x̄: 16.67% x̃: 16.67% 95% mean confidence interval for temps value: -2.09 1.09 95% mean confidence interval for temps %-change: -38.40% 18.40% Inconclusive result (value mean confidence interval includes 0). total immediates in shared programs: 141464 -> 141460 (<.01%) immediates in affected programs: 104 -> 100 (-3.85%) helped: 4 HURT: 3 helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4 helped stats (rel) min: 16.67% max: 50.00% x̄: 33.33% x̃: 33.33% HURT stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4 HURT stats (rel) min: 12.50% max: 100.00% x̄: 70.83% x̃: 100.00% 95% mean confidence interval for immediates value: -4.53 3.38 95% mean confidence interval for immediates %-change: -48.17% 70.79% Inconclusive result (value mean confidence interval includes 0). Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9039>
This commit is contained in:
Christian Gmeiner
Marge Bot
parent
1837135f7c
commit
dba692c618
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@ -1107,6 +1107,10 @@ etna_compile_shader_nir(struct etna_shader_variant *v)
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etna_optimize_loop(s);
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/* TODO: remove this extra run if nir_opt_peephole_select is able to handle ubo's. */
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if (OPT(s, etna_nir_lower_ubo_to_uniform))
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etna_optimize_loop(s);
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NIR_PASS_V(s, etna_lower_io, v);
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if (v->shader->specs->vs_need_z_div)
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@ -77,39 +77,6 @@ etna_lower_io(nir_shader *shader, struct etna_shader_variant *v)
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alu->src[0].swizzle[2] = 0;
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nir_instr_rewrite_src(instr, &intr->src[1], nir_src_for_ssa(ssa));
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} break;
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case nir_intrinsic_load_uniform: {
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/* convert indirect load_uniform to load_ubo when possible
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* this is required on HALTI5+ because address register is not implemented
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* address register loads also arent done optimally
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*/
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if (v->shader->specs->halti < 2 || nir_src_is_const(intr->src[0]))
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break;
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nir_intrinsic_instr *load_ubo =
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nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ubo);
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load_ubo->num_components = intr->num_components;
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nir_intrinsic_set_align(load_ubo, intr->dest.ssa.bit_size / 8, 0);
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nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
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load_ubo->num_components, 32, NULL);
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b.cursor = nir_before_instr(instr);
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load_ubo->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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load_ubo->src[1] = nir_src_for_ssa(nir_iadd(&b,
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nir_imul(&b, intr->src[0].ssa, nir_imm_int(&b, 16)),
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nir_imm_int(&b, nir_intrinsic_base(intr) * 16)));
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nir_builder_instr_insert(&b, &load_ubo->instr);
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nir_ssa_def_rewrite_uses(&intr->dest.ssa,
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nir_src_for_ssa(&load_ubo->dest.ssa));
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nir_instr_remove(&intr->instr);
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} break;
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case nir_intrinsic_load_ubo: {
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nir_const_value *idx = nir_src_as_const_value(intr->src[0]);
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assert(idx);
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/* offset index by 1, index 0 is used for converted load_uniform */
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b.cursor = nir_before_instr(instr);
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nir_instr_rewrite_src(instr, &intr->src[0],
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nir_src_for_ssa(nir_imm_int(&b, idx[0].u32 + 1)));
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} break;
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case nir_intrinsic_load_vertex_id:
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case nir_intrinsic_load_instance_id:
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/* detect use of vertex_id/instance_id */
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@ -1050,6 +1050,7 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
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.lower_fceil = !screen->specs.has_sign_floor_ceil,
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.lower_fsqrt = !screen->specs.has_sin_cos_sqrt,
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.lower_sincos = !screen->specs.has_sin_cos_sqrt,
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.lower_uniforms_to_ubo = screen->specs.halti >= 2,
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};
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/* apply debug options that disable individual features */
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