virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BIT
Previously, we ignored the the glUnmap(..) operation and flushed before we flush the cbuf. Now, let's just flush the data when we unmap. Neither method is optimal, for example: glMapBufferRange(.., 0, 100, GL_MAP_FLUSH_EXPLICIT_BIT) glFlushMappedBufferRange(.., 25, 30) glFlushMappedBufferRange(.., 65, 70) We'll end up flushing 25 --> 70. Maybe we can fix this later. v2: Add fixme comment in the code (Elie) Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
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@ -33,7 +33,6 @@ static void virgl_buffer_destroy(struct pipe_screen *screen,
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struct virgl_screen *vs = virgl_screen(screen);
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struct virgl_buffer *vbuf = virgl_buffer(buf);
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util_range_destroy(&vbuf->valid_buffer_range);
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vs->vws->resource_unref(vs->vws, vbuf->base.hw_res);
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FREE(vbuf);
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}
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@ -53,7 +52,7 @@ static void *virgl_buffer_transfer_map(struct pipe_context *ctx,
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bool readback;
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bool doflushwait = false;
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if ((usage & PIPE_TRANSFER_READ) && (vbuf->on_list == TRUE))
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if (usage & PIPE_TRANSFER_READ)
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doflushwait = true;
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else
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doflushwait = virgl_res_needs_flush_wait(vctx, &vbuf->base, usage);
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@ -92,14 +91,20 @@ static void virgl_buffer_transfer_unmap(struct pipe_context *ctx,
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struct virgl_buffer *vbuf = virgl_buffer(transfer->resource);
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if (trans->base.usage & PIPE_TRANSFER_WRITE) {
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if (!(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT)) {
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struct virgl_screen *vs = virgl_screen(ctx->screen);
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if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
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transfer->box.x += trans->range.start;
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transfer->box.width = trans->range.end - trans->range.start;
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trans->offset = transfer->box.x;
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}
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vctx->num_transfers++;
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vs->vws->transfer_put(vs->vws, vbuf->base.hw_res,
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&transfer->box, trans->base.stride, trans->l_stride, trans->offset, transfer->level);
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&transfer->box, trans->base.stride,
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trans->l_stride, trans->offset,
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transfer->level);
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}
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}
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virgl_resource_destroy_transfer(vctx, trans);
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}
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@ -108,20 +113,19 @@ static void virgl_buffer_transfer_flush_region(struct pipe_context *ctx,
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struct pipe_transfer *transfer,
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const struct pipe_box *box)
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{
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struct virgl_context *vctx = virgl_context(ctx);
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struct virgl_buffer *vbuf = virgl_buffer(transfer->resource);
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struct virgl_transfer *trans = virgl_transfer(transfer);
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if (!vbuf->on_list) {
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struct pipe_resource *res = NULL;
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list_addtail(&vbuf->flush_list, &vctx->to_flush_bufs);
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vbuf->on_list = TRUE;
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pipe_resource_reference(&res, &vbuf->base.u.b);
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}
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util_range_add(&vbuf->valid_buffer_range, transfer->box.x + box->x,
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transfer->box.x + box->x + box->width);
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/*
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* FIXME: This is not optimal. For example,
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*
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* glMapBufferRange(.., 0, 100, GL_MAP_FLUSH_EXPLICIT_BIT)
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* glFlushMappedBufferRange(.., 25, 30)
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* glFlushMappedBufferRange(.., 65, 70)
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*
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* We'll end up flushing 25 --> 70.
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*/
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util_range_add(&trans->range, box->x, box->x + box->width);
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vbuf->base.clean = FALSE;
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}
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@ -145,7 +149,6 @@ struct pipe_resource *virgl_buffer_create(struct virgl_screen *vs,
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buf->base.u.b.screen = &vs->base;
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buf->base.u.vtbl = &virgl_buffer_vtbl;
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pipe_reference_init(&buf->base.u.b.reference, 1);
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util_range_init(&buf->valid_buffer_range);
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virgl_resource_layout(&buf->base.u.b, &buf->metadata);
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vbind = pipe_to_virgl_bind(template->bind);
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@ -155,6 +158,5 @@ struct pipe_resource *virgl_buffer_create(struct virgl_screen *vs,
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template->width0, 1, 1, 1, 0, 0,
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buf->metadata.total_size);
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util_range_set_empty(&buf->valid_buffer_range);
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return &buf->base.u.b;
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}
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@ -60,29 +60,6 @@ uint32_t virgl_object_assign_handle(void)
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return ++next_handle;
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}
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static void virgl_buffer_flush(struct virgl_context *vctx,
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struct virgl_buffer *vbuf)
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{
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struct virgl_screen *rs = virgl_screen(vctx->base.screen);
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struct pipe_box box;
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assert(vbuf->on_list);
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box.height = 1;
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box.depth = 1;
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box.y = 0;
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box.z = 0;
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box.x = vbuf->valid_buffer_range.start;
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box.width = MIN2(vbuf->valid_buffer_range.end - vbuf->valid_buffer_range.start, vbuf->base.u.b.width0);
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vctx->num_transfers++;
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rs->vws->transfer_put(rs->vws, vbuf->base.hw_res,
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&box, 0, 0, box.x, 0);
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util_range_set_empty(&vbuf->valid_buffer_range);
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}
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static void virgl_attach_res_framebuffer(struct virgl_context *vctx)
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{
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struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
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@ -774,19 +751,11 @@ static void virgl_flush_from_st(struct pipe_context *ctx,
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enum pipe_flush_flags flags)
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{
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struct virgl_context *vctx = virgl_context(ctx);
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struct virgl_buffer *buf, *tmp;
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struct virgl_screen *rs = virgl_screen(ctx->screen);
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if (flags & PIPE_FLUSH_FENCE_FD)
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vctx->cbuf->needs_out_fence_fd = true;
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LIST_FOR_EACH_ENTRY_SAFE(buf, tmp, &vctx->to_flush_bufs, flush_list) {
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struct pipe_resource *res = &buf->base.u.b;
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virgl_buffer_flush(vctx, buf);
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list_del(&buf->flush_list);
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buf->on_list = FALSE;
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pipe_resource_reference(&res, NULL);
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}
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virgl_flush_eq(vctx, vctx, fence);
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if (vctx->cbuf->in_fence_fd != -1) {
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@ -1329,7 +1298,6 @@ struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
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virgl_init_query_functions(vctx);
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virgl_init_so_functions(vctx);
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list_inithead(&vctx->to_flush_bufs);
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slab_create_child(&vctx->transfer_pool, &rs->transfer_pool);
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vctx->primconvert = util_primconvert_create(&vctx->base, rs->caps.caps.v1.prim_mask);
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@ -75,7 +75,6 @@ struct virgl_context {
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struct pipe_resource *images[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
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int num_transfers;
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int num_draws;
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struct list_head to_flush_bufs;
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struct pipe_resource *atomic_buffers[PIPE_MAX_HW_ATOMIC_BUFFERS];
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@ -52,19 +52,6 @@ struct virgl_resource {
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struct virgl_buffer {
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struct virgl_resource base;
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struct list_head flush_list;
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boolean on_list;
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/* The buffer range which is initialized (with a write transfer,
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* streamout, DMA, or as a random access target). The rest of
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* the buffer is considered invalid and can be mapped unsynchronized.
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*
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* This allows unsychronized mapping of a buffer range which hasn't
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* been used yet. It's for applications which forget to use
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* the unsynchronized map flag and expect the driver to figure it out.
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*/
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struct util_range valid_buffer_range;
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struct virgl_resource_metadata metadata;
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};
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