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radeonsi/gfx9: don't ever flush the TC metadata cache 

The closed Vulkan driver doesn't do it either.

Also remove some old comments that aren't useful.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-06-20 18:26:12 +02:00
parent 920f20f039
commit db37c0be13
1 changed files with 3 additions and 10 deletions
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13
src/gallium/drivers/radeonsi/si_state_draw.c
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@ -971,22 +971,15 @@ void si_emit_cache_flush(struct si_context *sctx)
}
/* TC | TC_WB = invalidate L2 data
* TC_MD | TC_WB = invalidate L2 metadata
* TC_MD | TC_WB = invalidate L2 metadata (DCC, etc.)
* TC | TC_WB | TC_MD = invalidate L2 data & metadata
*
* The metadata cache must always be invalidated for coherency
* between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
*
* TC must be invalidated on GFX9 only if the CB/DB surface is
* not pipe-aligned. If the surface is RB-aligned, it might not
* strictly be pipe-aligned since RB alignment takes precendence.
*/
tc_flags = EVENT_TC_WB_ACTION_ENA |
EVENT_TC_MD_ACTION_ENA;
tc_flags = 0;
/* Ideally flush TC together with CB/DB. */
if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
tc_flags |= EVENT_TC_ACTION_ENA |
EVENT_TC_WB_ACTION_ENA |
EVENT_TCL1_ACTION_ENA;
/* Clear the flags. */