From db2bdc1dc37abc515a63ce174c6d201b23faa2e2 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 20 Jun 2022 13:23:14 -0400 Subject: [PATCH] pan/bi: Require ATEST coverage mask input in R60 In theory, ATEST can take any combination of registers for inputs. Experimentally, however, ATEST requires the coverage mask in R60. This avoids regressing the following dEQP tests, which write their coverage mask with pixel-frequency-shading but without writing to the depth/stencil buffer. dEQP-GLES31.functional.shaders.sample_variables.sample_mask.discard_half_per_pixel.* This issue is known to affect both Mali-G52 (v7) and Mali-G57 (v9). I am unsure if this is a silicon bug or just an obscure implementation detail. No shader-db changes. Signed-off-by: Alyssa Rosenzweig Cc: mesa-stable Part-of: --- src/panfrost/bifrost/bi_ra.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/panfrost/bifrost/bi_ra.c b/src/panfrost/bifrost/bi_ra.c index 2e3bf0fe332..e43f5ec2406 100644 --- a/src/panfrost/bifrost/bi_ra.c +++ b/src/panfrost/bifrost/bi_ra.c @@ -407,6 +407,17 @@ bi_allocate_registers(bi_context *ctx, bool *success, bool full_regs) assert(node < node_count); l->solutions[node] = 60; } + + /* Experimentally, it seems coverage masks inputs to ATEST must + * be in R60. Otherwise coverage mask writes do not work with + * early-ZS with pixel-frequency-shading (this combination of + * settings is legal if depth/stencil writes are disabled). + */ + if (ins->op == BI_OPCODE_ATEST) { + unsigned node = bi_get_node(ins->src[0]); + assert(node < node_count); + l->solutions[node] = 60; + } } bi_compute_interference(ctx, l, full_regs);