intel/compiler: Add backend compiler basics for Task/Mesh
Task/Mesh stages are CS-like stages, and include many builtins (e.g. workgroup ID/index) and intrinsics (e.g. workgroup memory primitives) originally present only in CS. This commit add two new stages (task and mesh) that 'inherit' from CS by embedding a brw_cs_prog_data in their own prog_data structure, so that CS functionality can be easily reused. They also currently use the same helpers to select the SIMD variant to use -- that was recently added for CS. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13661>
This commit is contained in:
parent
827cf65a26
commit
db23c41537
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@ -245,6 +245,8 @@ brw_prog_data_size(gl_shader_stage stage)
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[MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data),
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[MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data),
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[MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data),
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[MESA_SHADER_TASK] = sizeof(struct brw_task_prog_data),
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[MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_data),
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[MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_data),
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@ -267,6 +269,8 @@ brw_prog_key_size(gl_shader_stage stage)
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[MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key),
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[MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key),
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[MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key),
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[MESA_SHADER_TASK] = sizeof(struct brw_task_prog_key),
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[MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_key),
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[MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_key),
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@ -387,6 +387,16 @@ struct brw_gs_prog_key
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unsigned nr_userclip_plane_consts:4;
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};
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struct brw_task_prog_key
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{
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struct brw_base_prog_key base;
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};
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struct brw_mesh_prog_key
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{
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struct brw_base_prog_key base;
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};
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enum brw_sf_primitive {
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BRW_SF_PRIM_POINTS = 0,
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BRW_SF_PRIM_LINES = 1,
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@ -547,6 +557,8 @@ union brw_any_prog_key {
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struct brw_wm_prog_key wm;
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struct brw_cs_prog_key cs;
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struct brw_bs_prog_key bs;
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struct brw_task_prog_key task;
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struct brw_mesh_prog_key mesh;
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};
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/*
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@ -1444,6 +1456,24 @@ struct brw_mue_map {
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uint32_t per_vertex_pitch_dw;
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};
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struct brw_task_prog_data {
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struct brw_cs_prog_data base;
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struct brw_tue_map map;
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};
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enum brw_mesh_index_format {
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BRW_INDEX_FORMAT_U32,
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};
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struct brw_mesh_prog_data {
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struct brw_cs_prog_data base;
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struct brw_mue_map map;
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uint16_t primitive_type;
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enum brw_mesh_index_format index_format;
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};
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/* brw_any_prog_data is prog_data for any stage that maps to an API stage */
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union brw_any_prog_data {
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struct brw_stage_prog_data base;
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@ -1455,6 +1485,8 @@ union brw_any_prog_data {
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struct brw_wm_prog_data wm;
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struct brw_cs_prog_data cs;
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struct brw_bs_prog_data bs;
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struct brw_task_prog_data task;
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struct brw_mesh_prog_data mesh;
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};
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#define DEFINE_PROG_DATA_DOWNCAST(STAGE, CHECK) \
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@ -1486,6 +1518,9 @@ DEFINE_PROG_DATA_DOWNCAST(vue, prog_data->stage == MESA_SHADER_VERTEX ||
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prog_data->stage == MESA_SHADER_TESS_EVAL ||
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prog_data->stage == MESA_SHADER_GEOMETRY)
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DEFINE_PROG_DATA_DOWNCAST(task, prog_data->stage == MESA_SHADER_TASK)
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DEFINE_PROG_DATA_DOWNCAST(mesh, prog_data->stage == MESA_SHADER_MESH)
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/* These are not really brw_stage_prog_data. */
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DEFINE_PROG_DATA_DOWNCAST(ff_gs, true)
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DEFINE_PROG_DATA_DOWNCAST(clip, true)
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@ -1642,6 +1677,41 @@ brw_compile_clip(const struct brw_compiler *compiler,
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struct brw_vue_map *vue_map,
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unsigned *final_assembly_size);
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struct brw_compile_task_params {
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struct nir_shader *nir;
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const struct brw_task_prog_key *key;
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struct brw_task_prog_data *prog_data;
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struct brw_compile_stats *stats;
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char *error_str;
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void *log_data;
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};
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const unsigned *
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brw_compile_task(const struct brw_compiler *compiler,
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void *mem_ctx,
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struct brw_compile_task_params *params);
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struct brw_compile_mesh_params {
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struct nir_shader *nir;
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const struct brw_mesh_prog_key *key;
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struct brw_mesh_prog_data *prog_data;
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const struct brw_tue_map *tue_map;
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struct brw_compile_stats *stats;
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char *error_str;
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void *log_data;
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};
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const unsigned *
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brw_compile_mesh(const struct brw_compiler *compiler,
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void *mem_ctx,
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struct brw_compile_mesh_params *params);
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/**
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* Parameters for compiling a fragment shader.
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*
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@ -9567,6 +9567,112 @@ fs_visitor::run_bs(bool allow_spilling)
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return !failed;
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}
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bool
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fs_visitor::run_task(bool allow_spilling)
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{
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assert(stage == MESA_SHADER_TASK);
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/* Task Shader Payloads (SIMD8 and SIMD16)
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*
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* R0: Header
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* R1: Local_ID.X[0-7 or 0-15]
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* R2: Inline Parameter
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*
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* Task Shader Payloads (SIMD32)
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*
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* R0: Header
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* R1: Local_ID.X[0-15]
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* R2: Local_ID.X[16-31]
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* R3: Inline Parameter
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*
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* Local_ID.X values are 16 bits.
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*
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* Inline parameter is optional but always present since we use it to pass
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* the address to descriptors.
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*/
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payload.num_regs = dispatch_width == 32 ? 4 : 3;
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if (shader_time_index >= 0)
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emit_shader_time_begin();
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emit_nir_code();
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if (failed)
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return false;
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emit_cs_terminate();
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if (shader_time_index >= 0)
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emit_shader_time_end();
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calculate_cfg();
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optimize();
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assign_curb_setup();
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fixup_3src_null_dest();
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allocate_registers(allow_spilling);
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if (failed)
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return false;
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return !failed;
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}
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bool
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fs_visitor::run_mesh(bool allow_spilling)
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{
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assert(stage == MESA_SHADER_MESH);
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/* Mesh Shader Payloads (SIMD8 and SIMD16)
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*
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* R0: Header
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* R1: Local_ID.X[0-7 or 0-15]
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* R2: Inline Parameter
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*
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* Mesh Shader Payloads (SIMD32)
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*
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* R0: Header
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* R1: Local_ID.X[0-15]
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* R2: Local_ID.X[16-31]
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* R3: Inline Parameter
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*
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* Local_ID.X values are 16 bits.
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*
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* Inline parameter is optional but always present since we use it to pass
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* the address to descriptors.
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*/
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payload.num_regs = dispatch_width == 32 ? 4 : 3;
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if (shader_time_index >= 0)
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emit_shader_time_begin();
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emit_nir_code();
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if (failed)
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return false;
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emit_cs_terminate();
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if (shader_time_index >= 0)
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emit_shader_time_end();
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calculate_cfg();
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optimize();
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assign_curb_setup();
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fixup_3src_null_dest();
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allocate_registers(allow_spilling);
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if (failed)
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return false;
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return !failed;
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}
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static bool
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is_used_in_not_interp_frag_coord(nir_ssa_def *def)
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{
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@ -127,6 +127,8 @@ public:
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bool run_gs();
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bool run_cs(bool allow_spilling);
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bool run_bs(bool allow_spilling);
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bool run_task(bool allow_spilling);
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bool run_mesh(bool allow_spilling);
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void optimize();
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void allocate_registers(bool allow_spilling);
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void setup_fs_payload_gfx4();
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@ -254,6 +256,12 @@ public:
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nir_intrinsic_instr *instr);
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void nir_emit_bs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_task_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_mesh_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_task_mesh_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
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@ -453,6 +453,12 @@ fs_visitor::nir_emit_instr(nir_instr *instr)
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case MESA_SHADER_CALLABLE:
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nir_emit_bs_intrinsic(abld, nir_instr_as_intrinsic(instr));
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break;
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case MESA_SHADER_TASK:
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nir_emit_task_intrinsic(abld, nir_instr_as_intrinsic(instr));
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break;
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case MESA_SHADER_MESH:
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nir_emit_mesh_intrinsic(abld, nir_instr_as_intrinsic(instr));
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break;
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default:
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unreachable("unsupported shader stage");
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}
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@ -0,0 +1,263 @@
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/*
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* Copyright © 2021 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_compiler.h"
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#include "brw_fs.h"
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#include "brw_nir.h"
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#include "brw_private.h"
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#include "compiler/nir/nir_builder.h"
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#include "dev/intel_debug.h"
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using namespace brw;
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const unsigned *
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brw_compile_task(const struct brw_compiler *compiler,
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void *mem_ctx,
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struct brw_compile_task_params *params)
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{
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struct nir_shader *nir = params->nir;
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const struct brw_task_prog_key *key = params->key;
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struct brw_task_prog_data *prog_data = params->prog_data;
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const bool debug_enabled = INTEL_DEBUG(DEBUG_TASK);
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prog_data->base.base.stage = MESA_SHADER_TASK;
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prog_data->base.base.total_shared = nir->info.shared_size;
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prog_data->base.local_size[0] = nir->info.workgroup_size[0];
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prog_data->base.local_size[1] = nir->info.workgroup_size[1];
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prog_data->base.local_size[2] = nir->info.workgroup_size[2];
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const unsigned required_dispatch_width =
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brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type);
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fs_visitor *v[3] = {0};
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const char *error[3] = {0};
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for (unsigned simd = 0; simd < 3; simd++) {
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if (!brw_simd_should_compile(mem_ctx, simd, compiler->devinfo, &prog_data->base,
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required_dispatch_width, &error[simd]))
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continue;
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const unsigned dispatch_width = 8 << simd;
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nir_shader *shader = nir_shader_clone(mem_ctx, nir);
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brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */);
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NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);
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brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
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key->base.robust_buffer_access);
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v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
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&prog_data->base.base, shader, dispatch_width,
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-1 /* shader_time_index */, debug_enabled);
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if (prog_data->base.prog_mask) {
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unsigned first = ffs(prog_data->base.prog_mask) - 1;
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v[simd]->import_uniforms(v[first]);
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}
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const bool allow_spilling = !prog_data->base.prog_mask;
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if (v[simd]->run_task(allow_spilling))
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brw_simd_mark_compiled(simd, &prog_data->base, v[simd]->spilled_any_registers);
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else
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error[simd] = ralloc_strdup(mem_ctx, v[simd]->fail_msg);
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}
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int selected_simd = brw_simd_select(&prog_data->base);
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if (selected_simd < 0) {
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params->error_str = ralloc_asprintf(mem_ctx, "Can't compile shader: %s, %s and %s.\n",
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error[0], error[1], error[2]);;
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return NULL;
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}
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fs_visitor *selected = v[selected_simd];
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prog_data->base.prog_mask = 1 << selected_simd;
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fs_generator g(compiler, params->log_data, mem_ctx,
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&prog_data->base.base, false, MESA_SHADER_TASK);
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if (unlikely(debug_enabled)) {
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g.enable_debug(ralloc_asprintf(mem_ctx,
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"%s task shader %s",
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nir->info.label ? nir->info.label
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: "unnamed",
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nir->info.name));
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}
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g.generate_code(selected->cfg, selected->dispatch_width, selected->shader_stats,
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selected->performance_analysis.require(), params->stats);
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delete v[0];
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delete v[1];
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delete v[2];
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return g.get_assembly();
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}
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const unsigned *
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brw_compile_mesh(const struct brw_compiler *compiler,
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void *mem_ctx,
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struct brw_compile_mesh_params *params)
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{
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struct nir_shader *nir = params->nir;
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const struct brw_mesh_prog_key *key = params->key;
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struct brw_mesh_prog_data *prog_data = params->prog_data;
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const bool debug_enabled = INTEL_DEBUG(DEBUG_MESH);
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prog_data->base.base.stage = MESA_SHADER_MESH;
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prog_data->base.base.total_shared = nir->info.shared_size;
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prog_data->base.local_size[0] = nir->info.workgroup_size[0];
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prog_data->base.local_size[1] = nir->info.workgroup_size[1];
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prog_data->base.local_size[2] = nir->info.workgroup_size[2];
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prog_data->primitive_type = nir->info.mesh.primitive_type;
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/* TODO(mesh): Use other index formats (that are more compact) for optimization. */
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prog_data->index_format = BRW_INDEX_FORMAT_U32;
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const unsigned required_dispatch_width =
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brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type);
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fs_visitor *v[3] = {0};
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const char *error[3] = {0};
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for (int simd = 0; simd < 3; simd++) {
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if (!brw_simd_should_compile(mem_ctx, simd, compiler->devinfo, &prog_data->base,
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required_dispatch_width, &error[simd]))
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continue;
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const unsigned dispatch_width = 8 << simd;
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|
||||
nir_shader *shader = nir_shader_clone(mem_ctx, nir);
|
||||
brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */);
|
||||
|
||||
NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);
|
||||
|
||||
brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
|
||||
key->base.robust_buffer_access);
|
||||
|
||||
v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
|
||||
&prog_data->base.base, shader, dispatch_width,
|
||||
-1 /* shader_time_index */, debug_enabled);
|
||||
|
||||
if (prog_data->base.prog_mask) {
|
||||
unsigned first = ffs(prog_data->base.prog_mask) - 1;
|
||||
v[simd]->import_uniforms(v[first]);
|
||||
}
|
||||
|
||||
const bool allow_spilling = !prog_data->base.prog_mask;
|
||||
|
||||
if (v[simd]->run_mesh(allow_spilling))
|
||||
brw_simd_mark_compiled(simd, &prog_data->base, v[simd]->spilled_any_registers);
|
||||
else
|
||||
error[simd] = ralloc_strdup(mem_ctx, v[simd]->fail_msg);
|
||||
}
|
||||
|
||||
int selected_simd = brw_simd_select(&prog_data->base);
|
||||
if (selected_simd < 0) {
|
||||
params->error_str = ralloc_asprintf(mem_ctx, "Can't compile shader: %s, %s and %s.\n",
|
||||
error[0], error[1], error[2]);;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
fs_visitor *selected = v[selected_simd];
|
||||
prog_data->base.prog_mask = 1 << selected_simd;
|
||||
|
||||
fs_generator g(compiler, params->log_data, mem_ctx,
|
||||
&prog_data->base.base, false, MESA_SHADER_MESH);
|
||||
if (unlikely(debug_enabled)) {
|
||||
g.enable_debug(ralloc_asprintf(mem_ctx,
|
||||
"%s mesh shader %s",
|
||||
nir->info.label ? nir->info.label
|
||||
: "unnamed",
|
||||
nir->info.name));
|
||||
}
|
||||
|
||||
g.generate_code(selected->cfg, selected->dispatch_width, selected->shader_stats,
|
||||
selected->performance_analysis.require(), params->stats);
|
||||
|
||||
delete v[0];
|
||||
delete v[1];
|
||||
delete v[2];
|
||||
|
||||
return g.get_assembly();
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::nir_emit_task_intrinsic(const fs_builder &bld,
|
||||
nir_intrinsic_instr *instr)
|
||||
{
|
||||
assert(stage == MESA_SHADER_TASK);
|
||||
|
||||
switch (instr->intrinsic) {
|
||||
case nir_intrinsic_store_output:
|
||||
case nir_intrinsic_load_output:
|
||||
/* TODO(mesh): Task Output. */
|
||||
break;
|
||||
|
||||
default:
|
||||
nir_emit_task_mesh_intrinsic(bld, instr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::nir_emit_mesh_intrinsic(const fs_builder &bld,
|
||||
nir_intrinsic_instr *instr)
|
||||
{
|
||||
assert(stage == MESA_SHADER_MESH);
|
||||
|
||||
switch (instr->intrinsic) {
|
||||
case nir_intrinsic_load_input:
|
||||
/* TODO(mesh): Mesh Input. */
|
||||
break;
|
||||
|
||||
case nir_intrinsic_store_per_primitive_output:
|
||||
case nir_intrinsic_store_per_vertex_output:
|
||||
case nir_intrinsic_store_output:
|
||||
case nir_intrinsic_load_per_vertex_output:
|
||||
case nir_intrinsic_load_per_primitive_output:
|
||||
case nir_intrinsic_load_output:
|
||||
/* TODO(mesh): Mesh Output. */
|
||||
break;
|
||||
|
||||
default:
|
||||
nir_emit_task_mesh_intrinsic(bld, instr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::nir_emit_task_mesh_intrinsic(const fs_builder &bld,
|
||||
nir_intrinsic_instr *instr)
|
||||
{
|
||||
assert(stage == MESA_SHADER_MESH || stage == MESA_SHADER_TASK);
|
||||
|
||||
switch (instr->intrinsic) {
|
||||
default:
|
||||
nir_emit_cs_intrinsic(bld, instr);
|
||||
break;
|
||||
}
|
||||
}
|
|
@ -76,6 +76,7 @@ libintel_compiler_files = files(
|
|||
'brw_ir_performance.h',
|
||||
'brw_ir_performance.cpp',
|
||||
'brw_ir_vec4.h',
|
||||
'brw_mesh.cpp',
|
||||
'brw_nir.h',
|
||||
'brw_nir.c',
|
||||
'brw_nir_analyze_boolean_resolves.c',
|
||||
|
|
Loading…
Reference in New Issue