intel: Extend the force_y_tiling flag to allow forcing no tiling.
For a blit-uploaded temporary, it's faster on current hardware to memcpy the data into a linear CPU mapping than to go through the GTT. v2: Turn the not-fully-supported mask into 3 supported enum values. Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) Reviewed-by: Paul Berry <stereotype441@gmail.com> (v2) Reviewed-by: Chad Versace <chad.versace@linux.intel.com> (v2)
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@ -924,7 +924,7 @@ intel_renderbuffer_move_to_temp(struct intel_context *intel,
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width, height, depth,
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true,
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irb->mt->num_samples,
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false /* force_y_tiling */);
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INTEL_MIPTREE_TILING_ANY);
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if (intel->vtbl.is_hiz_depth_format(intel, new_mt->format)) {
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intel_miptree_alloc_hiz(intel, new_mt);
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@ -265,7 +265,7 @@ intel_miptree_create_layout(struct intel_context *intel,
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mt->logical_depth0,
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true,
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num_samples,
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false /* force_y_tiling */);
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INTEL_MIPTREE_TILING_ANY);
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if (!mt->stencil_mt) {
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intel_miptree_release(&mt);
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return NULL;
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@ -309,7 +309,7 @@ intel_miptree_choose_tiling(struct intel_context *intel,
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gl_format format,
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uint32_t width0,
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uint32_t num_samples,
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bool force_y_tiling,
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enum intel_miptree_tiling_mode requested,
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struct intel_mipmap_tree *mt)
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{
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@ -320,8 +320,17 @@ intel_miptree_choose_tiling(struct intel_context *intel,
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return I915_TILING_NONE;
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}
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if (force_y_tiling)
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/* Some usages may want only one type of tiling, like depth miptrees (Y
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* tiled), or temporary BOs for uploading data once (linear).
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*/
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switch (requested) {
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case INTEL_MIPTREE_TILING_ANY:
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break;
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case INTEL_MIPTREE_TILING_Y:
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return I915_TILING_Y;
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case INTEL_MIPTREE_TILING_NONE:
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return I915_TILING_NONE;
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}
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if (num_samples > 1) {
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/* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
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@ -375,7 +384,7 @@ intel_miptree_create(struct intel_context *intel,
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GLuint depth0,
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bool expect_accelerated_upload,
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GLuint num_samples,
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bool force_y_tiling)
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enum intel_miptree_tiling_mode requested_tiling)
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{
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struct intel_mipmap_tree *mt;
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gl_format tex_format = format;
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@ -441,7 +450,7 @@ intel_miptree_create(struct intel_context *intel,
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}
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uint32_t tiling = intel_miptree_choose_tiling(intel, format, width0,
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num_samples, force_y_tiling,
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num_samples, requested_tiling,
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mt);
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bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X);
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@ -570,7 +579,7 @@ intel_miptree_create_for_renderbuffer(struct intel_context *intel,
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mt = intel_miptree_create(intel, GL_TEXTURE_2D, format, 0, 0,
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width, height, depth, true, num_samples,
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false /* force_y_tiling */);
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INTEL_MIPTREE_TILING_ANY);
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if (!mt)
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goto fail;
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@ -1008,7 +1017,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
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mt->logical_depth0,
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true,
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0 /* num_samples */,
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true /* force_y_tiling */);
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INTEL_MIPTREE_TILING_Y);
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/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
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*
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@ -1089,7 +1098,7 @@ intel_miptree_alloc_hiz(struct intel_context *intel,
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mt->logical_depth0,
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true,
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mt->num_samples,
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false /* force_y_tiling */);
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INTEL_MIPTREE_TILING_ANY);
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if (!mt->hiz_mt)
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return false;
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@ -387,7 +387,11 @@ struct intel_mipmap_tree
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GLuint refcount;
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};
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enum intel_miptree_tiling_mode {
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INTEL_MIPTREE_TILING_ANY,
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INTEL_MIPTREE_TILING_Y,
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INTEL_MIPTREE_TILING_NONE,
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};
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struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
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GLenum target,
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@ -399,7 +403,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
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GLuint depth0,
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bool expect_accelerated_upload,
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GLuint num_samples,
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bool force_y_tiling);
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enum intel_miptree_tiling_mode);
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struct intel_mipmap_tree *
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intel_miptree_create_layout(struct intel_context *intel,
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@ -103,7 +103,7 @@ intel_miptree_create_for_teximage(struct intel_context *intel,
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depth,
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expect_accelerated_upload,
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intelImage->base.Base.NumSamples,
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false /* force_y_tiling */);
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INTEL_MIPTREE_TILING_ANY);
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}
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/* XXX: Do this for TexSubImage also:
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@ -106,7 +106,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
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depth,
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true,
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0 /* num_samples */,
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false /* force_y_tiling */);
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INTEL_MIPTREE_TILING_ANY);
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if (!intelObj->mt)
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return false;
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}
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