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intel: Extend the force_y_tiling flag to allow forcing no tiling. 

For a blit-uploaded temporary, it's faster on current hardware to memcpy
the data into a linear CPU mapping than to go through the GTT.

v2: Turn the not-fully-supported mask into 3 supported enum values.

Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Reviewed-by: Paul Berry <stereotype441@gmail.com> (v2)
Reviewed-by: Chad Versace <chad.versace@linux.intel.com> (v2)
This commit is contained in:
Eric Anholt 2013-05-23 16:08:22 -07:00
parent 045612c90e
commit da2880bea0
5 changed files with 26 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mesa/drivers/dri/intel/intel_fbo.c
View File

@ -924,7 +924,7 @@ intel_renderbuffer_move_to_temp(struct intel_context *intel,
width, height, depth,
true,
irb->mt->num_samples,
false /* force_y_tiling */);
INTEL_MIPTREE_TILING_ANY);
if (intel->vtbl.is_hiz_depth_format(intel, new_mt->format)) {
intel_miptree_alloc_hiz(intel, new_mt);

25
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
View File

@ -265,7 +265,7 @@ intel_miptree_create_layout(struct intel_context *intel,
mt->logical_depth0,
true,
num_samples,
false /* force_y_tiling */);
INTEL_MIPTREE_TILING_ANY);
if (!mt->stencil_mt) {
intel_miptree_release(&mt);
return NULL;
@ -309,7 +309,7 @@ intel_miptree_choose_tiling(struct intel_context *intel,
gl_format format,
uint32_t width0,
uint32_t num_samples,
bool force_y_tiling,
enum intel_miptree_tiling_mode requested,
struct intel_mipmap_tree *mt)
{
@ -320,8 +320,17 @@ intel_miptree_choose_tiling(struct intel_context *intel,
return I915_TILING_NONE;
}
if (force_y_tiling)
/* Some usages may want only one type of tiling, like depth miptrees (Y
* tiled), or temporary BOs for uploading data once (linear).
*/
switch (requested) {
case INTEL_MIPTREE_TILING_ANY:
break;
case INTEL_MIPTREE_TILING_Y:
return I915_TILING_Y;
case INTEL_MIPTREE_TILING_NONE:
return I915_TILING_NONE;
}
if (num_samples > 1) {
/* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
@ -375,7 +384,7 @@ intel_miptree_create(struct intel_context *intel,
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
bool force_y_tiling)
enum intel_miptree_tiling_mode requested_tiling)
{
struct intel_mipmap_tree *mt;
gl_format tex_format = format;
@ -441,7 +450,7 @@ intel_miptree_create(struct intel_context *intel,
}
uint32_t tiling = intel_miptree_choose_tiling(intel, format, width0,
num_samples, force_y_tiling,
num_samples, requested_tiling,
mt);
bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X);
@ -570,7 +579,7 @@ intel_miptree_create_for_renderbuffer(struct intel_context *intel,
mt = intel_miptree_create(intel, GL_TEXTURE_2D, format, 0, 0,
width, height, depth, true, num_samples,
false /* force_y_tiling */);
INTEL_MIPTREE_TILING_ANY);
if (!mt)
goto fail;
@ -1008,7 +1017,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
mt->logical_depth0,
true,
0 /* num_samples */,
true /* force_y_tiling */);
INTEL_MIPTREE_TILING_Y);
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
@ -1089,7 +1098,7 @@ intel_miptree_alloc_hiz(struct intel_context *intel,
mt->logical_depth0,
true,
mt->num_samples,
false /* force_y_tiling */);
INTEL_MIPTREE_TILING_ANY);
if (!mt->hiz_mt)
return false;

8
src/mesa/drivers/dri/intel/intel_mipmap_tree.h
View File

@ -387,7 +387,11 @@ struct intel_mipmap_tree
GLuint refcount;
};
enum intel_miptree_tiling_mode {
INTEL_MIPTREE_TILING_ANY,
INTEL_MIPTREE_TILING_Y,
INTEL_MIPTREE_TILING_NONE,
};
struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
GLenum target,
@ -399,7 +403,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
bool force_y_tiling);
enum intel_miptree_tiling_mode);
struct intel_mipmap_tree *
intel_miptree_create_layout(struct intel_context *intel,

2
src/mesa/drivers/dri/intel/intel_tex_image.c
View File

@ -103,7 +103,7 @@ intel_miptree_create_for_teximage(struct intel_context *intel,
depth,
expect_accelerated_upload,
intelImage->base.Base.NumSamples,
false /* force_y_tiling */);
INTEL_MIPTREE_TILING_ANY);
}
/* XXX: Do this for TexSubImage also:

2
src/mesa/drivers/dri/intel/intel_tex_validate.c
View File

@ -106,7 +106,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
depth,
true,
0 /* num_samples */,
false /* force_y_tiling */);
INTEL_MIPTREE_TILING_ANY);
if (!intelObj->mt)
return false;
}