i965/barrier: Do the correct flushes for framebuffer access
Framebuffer access includes framebuffer reads so we need to invalidate the texture cache. We do not, however, need to flush the depth cache because you cannot do bind a depth texture as an image. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
parent
45991479a3
commit
d9ed4f6c32
|
@ -274,7 +274,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
|
|||
PIPE_CONTROL_RENDER_TARGET_FLUSH);
|
||||
|
||||
if (barriers & GL_FRAMEBUFFER_BARRIER_BIT)
|
||||
bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |
|
||||
bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
|
||||
PIPE_CONTROL_RENDER_TARGET_FLUSH);
|
||||
|
||||
/* Typed surface messages are handled by the render cache on IVB, so we
|
||||
|
|
Loading…
Reference in New Issue