freedreno: Decode a650+ CP_START_BIN/CP_END_BIN packets
The blob uses them for GMEM renderpasses. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12184>
This commit is contained in:
Connor Abbott
Marge Bot
parent
726fdf3385
commit
d9c90eee8b
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@ -213,8 +213,8 @@ CP_SET_DRAW_INIT_FLAGS:
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CP_SCRATCH_TO_REG:
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CP_DRAW_PRED_SET:
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CP_MEM_WRITE_CNTR:
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UNKN80:
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CP_SET_BIN_SELECT:
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CP_START_BIN:
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CP_END_BIN:
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CP_WAIT_REG_EQ:
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CP_SMMU_TABLE_UPDATE:
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UNKN84:
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@ -274,8 +274,8 @@ CP_SET_DRAW_INIT_FLAGS:
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CP_SCRATCH_TO_REG:
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CP_DRAW_PRED_SET:
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CP_MEM_WRITE_CNTR:
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UNKN80:
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CP_SET_BIN_SELECT:
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CP_START_BIN:
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CP_END_BIN:
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CP_WAIT_REG_EQ:
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CP_SMMU_TABLE_UPDATE:
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UNKN84:
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@ -2189,6 +2189,50 @@ cp_indirect(uint32_t *dwords, uint32_t sizedwords, int level)
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}
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}
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static void
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cp_start_bin(uint32_t *dwords, uint32_t sizedwords, int level)
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{
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uint64_t ibaddr;
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uint32_t ibsize;
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uint32_t loopcount;
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uint32_t *ptr = NULL;
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loopcount = dwords[0];
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ibaddr = dwords[1];
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ibaddr |= ((uint64_t)dwords[2]) << 32;
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ibsize = dwords[3];
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/* map gpuaddr back to hostptr: */
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ptr = hostptr(ibaddr);
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if (ptr) {
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/* If the GPU hung within the target IB, the trigger point will be
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* just after the current CP_START_BIN. Because the IB is
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* executed but never returns. Account for this by checking if
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* the IB returned:
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*/
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highlight_gpuaddr(gpuaddr(&dwords[5]));
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/* TODO: we should duplicate the body of the loop after each bin, so
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* that draws get the correct state. We should also figure out if there
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* are any registers that can tell us what bin we're in when we hang so
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* that crashdec points to the right place.
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*/
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ib++;
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for (uint32_t i = 0; i < loopcount; i++) {
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ibs[ib].base = ibaddr;
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ibs[ib].size = ibsize;
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printf("%sbin %u\n", levels[level], i);
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dump_commands(ptr, ibsize, level);
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ibaddr += ibsize;
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ptr += ibsize;
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}
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ib--;
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} else {
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fprintf(stderr, "could not find: %016" PRIx64 " (%d)\n", ibaddr, ibsize);
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}
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}
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static void
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cp_wfi(uint32_t *dwords, uint32_t sizedwords, int level)
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{
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@ -2646,6 +2690,8 @@ static const struct type3_op {
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CP(REG_WRITE, cp_reg_write),
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CP(SET_CTXSWITCH_IB, cp_set_ctxswitch_ib),
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CP(START_BIN, cp_start_bin),
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};
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static void
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@ -240,7 +240,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<doc>sets the 64-bit BIN_MASK register in the PFP</doc>
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<value name="CP_SET_BIN_MASK" value="0x50" varset="chip" variants="A2XX-A4XX"/>
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<doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
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<value name="CP_SET_BIN_SELECT" value="0x51"/>
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<value name="CP_SET_BIN_SELECT" value="0x51" varset="chip" variants="A2XX-A4XX"/>
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<doc>updates the current context, if needed</doc>
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<value name="CP_CONTEXT_UPDATE" value="0x5e"/>
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<doc>generate interrupt from the command stream</doc>
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@ -478,6 +478,20 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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-->
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<value name="CP_REG_WRITE" value="0x6d" varset="chip" variants="A6XX"/>
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<doc>
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These first appear in a650_sqe.bin. They can in theory be used
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to loop any sequence of IB1 commands, but in practice they are
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used to loop over bins. There is a fixed-size per-iteration
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prefix, used to set per-bin state, and then the following IB1
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commands are executed until CP_END_BIN which are always the same
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for each iteration and usually contain a list of
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CP_INDIRECT_BUFFER calls to IB2 commands which setup state and
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execute restore/draw/save commands. This replaces the previous
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technique of just repeating the CP_INDIRECT_BUFFER calls and
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"unrolling" the loop.
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</doc>
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<value name="CP_START_BIN" value="0x50" varset="chip" variants="A6XX"/>
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<value name="CP_END_BIN" value="0x51" varset="chip" variants="A6XX"/>
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</enum>
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@ -1758,5 +1772,21 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
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</reg32>
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</domain>
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<domain name="CP_START_BIN" width="32">
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<reg32 offset="0" name="BIN_COUNT" type="uint"/>
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<reg64 offset="1" name="PREFIX_ADDR" type="address"/>
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<reg32 offset="3" name="PREFIX_DWORDS">
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<doc>
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Size of prefix for each bin. For each bin index i, the
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prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are
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executed in an IB2 before the IB1 commands following
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this packet.
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</doc>
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</reg32>
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<reg32 offset="4" name="BODY_DWORDS">
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<doc>Number of dwords after this packet until CP_END_BIN</doc>
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</reg32>
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</domain>
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</database>
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