i965: Integrate precise trig into configuration infrastructure
With this change, to enable precise SIN and COS instructions on Intel hardware, one can put <option name="precise_trig" value="true"/> in the proper drirc file. V2: Make option name more generic Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
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@ -158,6 +158,11 @@ DRI_CONF_OPT_BEGIN_B(force_s3tc_enable, def) \
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DRI_CONF_DESC(en,gettext("Enable S3TC texture compression even if software support is not available")) \
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DRI_CONF_OPT_END
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#define DRI_CONF_PRECISE_TRIG(def) \
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DRI_CONF_OPT_BEGIN_B(precise_trig, def) \
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DRI_CONF_DESC(en,gettext("Prefer accuracy over performance in trig functions")) \
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DRI_CONF_OPT_END
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#define DRI_CONF_COLOR_REDUCTION_ROUND 0
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#define DRI_CONF_COLOR_REDUCTION_DITHER 1
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#define DRI_CONF_COLOR_REDUCTION(def) \
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@ -103,8 +103,6 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
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brw_fs_alloc_reg_sets(compiler);
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brw_vec4_alloc_reg_set(compiler);
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compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
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compiler->scalar_stage[MESA_SHADER_VERTEX] =
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devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
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compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
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@ -803,6 +803,9 @@ brw_process_driconf_options(struct brw_context *brw)
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brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile");
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brw->intelScreen->compiler->precise_trig =
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driQueryOptionb(&brw->optionCache, "precise_trig");
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ctx->Const.ForceGLSLExtensionsWarn =
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driQueryOptionb(options, "force_glsl_extensions_warn");
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@ -65,6 +65,8 @@ DRI_CONF_BEGIN
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DRI_CONF_SECTION_QUALITY
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DRI_CONF_FORCE_S3TC_ENABLE("false")
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DRI_CONF_PRECISE_TRIG("false")
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DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
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DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the "
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"given integer. If negative, then do not clamp.")
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