diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp
index dcc85a92e2f..5923fea9589 100644
--- a/src/amd/compiler/aco_ir.cpp
+++ b/src/amd/compiler/aco_ir.cpp
@@ -525,12 +525,18 @@ get_reduction_identity(ReduceOp op, unsigned idx)
 bool
 needs_exec_mask(const Instruction* instr)
 {
-   if (instr->isSALU() || instr->isBranch())
+   if (instr->isVALU()) {
+      return instr->opcode != aco_opcode::v_readlane_b32 &&
+             instr->opcode != aco_opcode::v_readlane_b32_e64 &&
+             instr->opcode != aco_opcode::v_writelane_b32 &&
+             instr->opcode != aco_opcode::v_writelane_b32_e64;
+   }
+
+   if (instr->isVMEM() || instr->isFlatLike())
+      return true;
+
+   if (instr->isSALU() || instr->isBranch() || instr->isSMEM() || instr->isBarrier())
       return instr->reads_exec();
-   if (instr->isSMEM())
-      return false;
-   if (instr->isBarrier())
-      return false;
 
    if (instr->isPseudo()) {
       switch (instr->opcode) {
@@ -543,22 +549,16 @@ needs_exec_mask(const Instruction* instr)
             if (def.getTemp().type() == RegType::vgpr)
                return true;
          }
-         return false;
+         return instr->reads_exec();
       case aco_opcode::p_spill:
       case aco_opcode::p_reload:
       case aco_opcode::p_logical_start:
       case aco_opcode::p_logical_end:
-      case aco_opcode::p_startpgm: return false;
+      case aco_opcode::p_startpgm: return instr->reads_exec();
       default: break;
       }
    }
 
-   if (instr->opcode == aco_opcode::v_readlane_b32 ||
-       instr->opcode == aco_opcode::v_readlane_b32_e64 ||
-       instr->opcode == aco_opcode::v_writelane_b32 ||
-       instr->opcode == aco_opcode::v_writelane_b32_e64)
-      return false;
-
    return true;
 }