radv: Implement DGC cmdbuffer generation.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17269>
This commit is contained in:
Bas Nieuwenhuizen
Marge Bot
parent
37a619f517
commit
d7bd9db9fc
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@ -1055,7 +1055,7 @@ radv_CreateIndirectCommandsLayoutNV(VkDevice _device,
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layout->vbo_offsets[pCreateInfo->pTokens[i].vertexBindingUnit] =
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pCreateInfo->pTokens[i].offset;
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if (pCreateInfo->pTokens[i].vertexDynamicStride)
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layout->vbo_offsets[pCreateInfo->pTokens[i].vertexBindingUnit] |= 1u << 15;
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layout->vbo_offsets[pCreateInfo->pTokens[i].vertexBindingUnit] |= DGC_DYNAMIC_STRIDE;
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break;
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case VK_INDIRECT_COMMANDS_TOKEN_TYPE_PUSH_CONSTANT_NV:
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for (unsigned j = pCreateInfo->pTokens[i].pushconstantOffset / 4, k = 0;
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@ -1116,3 +1116,274 @@ radv_GetGeneratedCommandsMemoryRequirementsNV(
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pMemoryRequirements->memoryRequirements.size =
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align(cmd_buf_size + upload_buf_size, pMemoryRequirements->memoryRequirements.alignment);
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}
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void
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radv_CmdPreprocessGeneratedCommandsNV(VkCommandBuffer commandBuffer,
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const VkGeneratedCommandsInfoNV *pGeneratedCommandsInfo)
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{
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/* Can't do anything here as we depend on some dynamic state in some cases that we only know
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* at draw time. */
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}
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/* Always need to call this directly before draw due to dependence on bound state. */
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void
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radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer,
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const VkGeneratedCommandsInfoNV *pGeneratedCommandsInfo)
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{
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VK_FROM_HANDLE(radv_indirect_command_layout, layout,
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pGeneratedCommandsInfo->indirectCommandsLayout);
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VK_FROM_HANDLE(radv_pipeline, pipeline, pGeneratedCommandsInfo->pipeline);
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VK_FROM_HANDLE(radv_buffer, prep_buffer, pGeneratedCommandsInfo->preprocessBuffer);
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struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline);
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struct radv_meta_saved_state saved_state;
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struct radv_buffer token_buffer;
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uint32_t cmd_stride, upload_stride;
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radv_get_sequence_size(layout, graphics_pipeline, &cmd_stride, &upload_stride);
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unsigned cmd_buf_size =
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radv_align_cmdbuf_size(cmd_stride * pGeneratedCommandsInfo->sequencesCount);
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unsigned vb_size = layout->bind_vbo_mask ? util_bitcount(graphics_pipeline->vb_desc_usage_mask) * 24 : 0;
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unsigned const_size = graphics_pipeline->base.push_constant_size +
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16 * graphics_pipeline->base.dynamic_offset_count +
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sizeof(layout->push_constant_offsets) + ARRAY_SIZE(graphics_pipeline->base.shaders) * 12;
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if (!layout->push_constant_mask)
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const_size = 0;
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unsigned scissor_size = (8 + 2 * cmd_buffer->state.dynamic.scissor.count) * 4;
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if (!layout->binds_state || !cmd_buffer->state.dynamic.scissor.count ||
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!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
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scissor_size = 0;
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unsigned upload_size = MAX2(vb_size + const_size + scissor_size, 16);
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void *upload_data;
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unsigned upload_offset;
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if (!radv_cmd_buffer_upload_alloc(cmd_buffer, upload_size, &upload_offset, &upload_data)) {
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cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
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return;
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}
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void *upload_data_base = upload_data;
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radv_buffer_init(&token_buffer, cmd_buffer->device, cmd_buffer->upload.upload_bo, upload_size,
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upload_offset);
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uint64_t upload_addr = radv_buffer_get_va(prep_buffer->bo) + prep_buffer->offset +
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pGeneratedCommandsInfo->preprocessOffset;
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uint16_t vtx_base_sgpr =
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(cmd_buffer->state.graphics_pipeline->vtx_base_sgpr - SI_SH_REG_OFFSET) >> 2;
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if (cmd_buffer->state.graphics_pipeline->uses_drawid)
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vtx_base_sgpr |= DGC_USES_DRAWID;
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if (cmd_buffer->state.graphics_pipeline->uses_baseinstance)
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vtx_base_sgpr |= DGC_USES_BASEINSTANCE;
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uint16_t vbo_sgpr =
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((radv_lookup_user_sgpr(&graphics_pipeline->base, MESA_SHADER_VERTEX, AC_UD_VS_VERTEX_BUFFERS)->sgpr_idx * 4 +
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graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX]) -
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SI_SH_REG_OFFSET) >>
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2;
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struct radv_dgc_params params = {
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.cmd_buf_stride = cmd_stride,
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.cmd_buf_size = cmd_buf_size,
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.upload_addr = (uint32_t)upload_addr,
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.upload_stride = upload_stride,
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.sequence_count = pGeneratedCommandsInfo->sequencesCount,
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.stream_stride = layout->input_stride,
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.draw_indexed = layout->indexed,
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.draw_params_offset = layout->draw_params_offset,
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.base_index_size =
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layout->binds_index_buffer ? 0 : radv_get_vgt_index_size(cmd_buffer->state.index_type),
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.vtx_base_sgpr = vtx_base_sgpr,
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.max_index_count = cmd_buffer->state.max_index_count,
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.index_buffer_offset = layout->index_buffer_offset,
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.vbo_reg = vbo_sgpr,
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.ibo_type_32 = layout->ibo_type_32,
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.ibo_type_8 = layout->ibo_type_8,
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.emit_state = layout->binds_state,
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.pa_su_sc_mode_cntl_base = radv_get_pa_su_sc_mode_cntl(cmd_buffer) & C_028814_FACE,
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.state_offset = layout->state_offset,
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};
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if (layout->bind_vbo_mask) {
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radv_write_vertex_descriptors(cmd_buffer, graphics_pipeline, true, upload_data);
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uint32_t *vbo_info = (uint32_t *)((char *)upload_data + graphics_pipeline->vb_desc_alloc_size);
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struct radv_shader *vs_shader = radv_get_shader(&graphics_pipeline->base, MESA_SHADER_VERTEX);
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const struct radv_vs_input_state *vs_state =
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vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;
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uint32_t mask = graphics_pipeline->vb_desc_usage_mask;
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unsigned idx = 0;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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unsigned binding =
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vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i]
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: (graphics_pipeline->use_per_attribute_vb_descs ? graphics_pipeline->attrib_bindings[i] : i);
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uint32_t attrib_end =
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vs_state ? vs_state->offsets[i] + vs_state->format_sizes[i] : graphics_pipeline->attrib_ends[i];
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params.vbo_bind_mask |= ((layout->bind_vbo_mask >> binding) & 1u) << idx;
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vbo_info[2 * idx] = ((graphics_pipeline->use_per_attribute_vb_descs ? 1u : 0u) << 31) |
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(vs_state ? vs_state->offsets[i] << 16 : 0) |
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layout->vbo_offsets[binding];
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vbo_info[2 * idx + 1] = graphics_pipeline->attrib_index_offset[i] | (attrib_end << 16);
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++idx;
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}
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params.vbo_cnt = idx | (vs_state ? DGC_DYNAMIC_VERTEX_INPUT : 0);
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upload_data = (char *)upload_data + vb_size;
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}
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if (layout->push_constant_mask) {
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uint32_t *desc = upload_data;
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upload_data = (char *)upload_data + ARRAY_SIZE(graphics_pipeline->base.shaders) * 12;
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unsigned idx = 0;
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for (unsigned i = 0; i < ARRAY_SIZE(graphics_pipeline->base.shaders); ++i) {
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if (!graphics_pipeline->base.shaders[i])
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continue;
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struct radv_userdata_locations *locs = &graphics_pipeline->base.shaders[i]->info.user_sgprs_locs;
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if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0)
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params.const_copy = 1;
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if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0 ||
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locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) {
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unsigned upload_sgpr = 0;
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unsigned inline_sgpr = 0;
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if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0) {
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upload_sgpr =
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(graphics_pipeline->base.user_data_0[i] + 4 * locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx -
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SI_SH_REG_OFFSET) >>
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2;
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}
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if (locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) {
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inline_sgpr = (graphics_pipeline->base.user_data_0[i] +
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4 * locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx -
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SI_SH_REG_OFFSET) >>
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2;
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desc[idx * 3 + 1] = graphics_pipeline->base.shaders[i]->info.inline_push_constant_mask;
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desc[idx * 3 + 2] = graphics_pipeline->base.shaders[i]->info.inline_push_constant_mask >> 32;
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}
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desc[idx * 3] = upload_sgpr | (inline_sgpr << 16);
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++idx;
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}
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}
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params.push_constant_shader_cnt = idx;
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params.const_copy_size = graphics_pipeline->base.push_constant_size +
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16 * graphics_pipeline->base.dynamic_offset_count;
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params.push_constant_mask = layout->push_constant_mask;
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memcpy(upload_data, layout->push_constant_offsets, sizeof(layout->push_constant_offsets));
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upload_data = (char *)upload_data + sizeof(layout->push_constant_offsets);
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memcpy(upload_data, cmd_buffer->push_constants, graphics_pipeline->base.push_constant_size);
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upload_data = (char *)upload_data + graphics_pipeline->base.push_constant_size;
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struct radv_descriptor_state *descriptors_state =
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radv_get_descriptors_state(cmd_buffer, pGeneratedCommandsInfo->pipelineBindPoint);
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memcpy(upload_data, descriptors_state->dynamic_buffers, 16 * graphics_pipeline->base.dynamic_offset_count);
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upload_data = (char *)upload_data + 16 * graphics_pipeline->base.dynamic_offset_count;
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}
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if (scissor_size) {
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params.scissor_offset = (char*)upload_data - (char*)upload_data_base;
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params.scissor_count = scissor_size / 4;
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struct radeon_cmdbuf scissor_cs = {
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.buf = upload_data,
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.cdw = 0,
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.max_dw = scissor_size / 4
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};
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radv_write_scissors(cmd_buffer, &scissor_cs);
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assert(scissor_cs.cdw * 4 == scissor_size);
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upload_data = (char *)upload_data + scissor_size;
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}
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VkWriteDescriptorSet ds_writes[5];
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VkDescriptorBufferInfo buf_info[ARRAY_SIZE(ds_writes)];
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int ds_cnt = 0;
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buf_info[ds_cnt] = (VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(&token_buffer),
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.offset = 0,
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.range = upload_size};
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ds_writes[ds_cnt] = (VkWriteDescriptorSet){.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = DGC_DESC_PARAMS,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &buf_info[ds_cnt]};
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++ds_cnt;
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buf_info[ds_cnt] = (VkDescriptorBufferInfo){.buffer = pGeneratedCommandsInfo->preprocessBuffer,
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.offset = pGeneratedCommandsInfo->preprocessOffset,
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.range = pGeneratedCommandsInfo->preprocessSize};
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ds_writes[ds_cnt] = (VkWriteDescriptorSet){.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = DGC_DESC_PREPARE,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &buf_info[ds_cnt]};
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++ds_cnt;
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if (pGeneratedCommandsInfo->streamCount > 0) {
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buf_info[ds_cnt] =
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(VkDescriptorBufferInfo){.buffer = pGeneratedCommandsInfo->pStreams[0].buffer,
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.offset = pGeneratedCommandsInfo->pStreams[0].offset,
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.range = VK_WHOLE_SIZE};
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ds_writes[ds_cnt] =
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(VkWriteDescriptorSet){.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = DGC_DESC_STREAM,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &buf_info[ds_cnt]};
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++ds_cnt;
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}
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if (pGeneratedCommandsInfo->sequencesCountBuffer != VK_NULL_HANDLE) {
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buf_info[ds_cnt] =
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(VkDescriptorBufferInfo){.buffer = pGeneratedCommandsInfo->sequencesCountBuffer,
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.offset = pGeneratedCommandsInfo->sequencesCountOffset,
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.range = VK_WHOLE_SIZE};
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ds_writes[ds_cnt] =
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(VkWriteDescriptorSet){.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = DGC_DESC_COUNT,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &buf_info[ds_cnt]};
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++ds_cnt;
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params.sequence_count = UINT32_MAX;
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}
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radv_meta_save(
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&saved_state, cmd_buffer,
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RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_CONSTANTS);
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
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cmd_buffer->device->meta_state.dgc_prepare.pipeline);
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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cmd_buffer->device->meta_state.dgc_prepare.p_layout,
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VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(params), ¶ms);
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radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
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cmd_buffer->device->meta_state.dgc_prepare.p_layout, 0, ds_cnt,
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ds_writes);
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unsigned block_count = MAX2(1, round_up_u32(pGeneratedCommandsInfo->sequencesCount, 64));
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radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
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radv_buffer_finish(&token_buffer);
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radv_meta_restore(&saved_state, cmd_buffer);
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cmd_buffer->state.flush_bits |=
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RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_L2;
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}
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@ -3019,6 +3019,9 @@ struct radv_indirect_command_layout {
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uint32_t radv_get_indirect_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);
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void radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer,
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const VkGeneratedCommandsInfoNV *pGeneratedCommandsInfo);
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uint64_t radv_get_current_time(void);
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static inline uint32_t
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