anv: Implement VK_KHR_pipeline_executable_properties
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
parent
67cb55ad11
commit
d787a2d05e
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@ -1126,6 +1126,13 @@ void anv_GetPhysicalDeviceFeatures2(
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
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VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
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(VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
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features->pipelineExecutableInfo = true;
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
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VkPhysicalDeviceProtectedMemoryFeatures *features = (void *)ext;
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features->protectedMemory = false;
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@ -101,6 +101,7 @@ EXTENSIONS = [
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Extension('VK_KHR_maintenance2', 1, True),
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Extension('VK_KHR_maintenance3', 1, True),
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Extension('VK_KHR_multiview', 1, True),
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Extension('VK_KHR_pipeline_executable_properties', 1, True),
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Extension('VK_KHR_push_descriptor', 1, True),
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Extension('VK_KHR_relaxed_block_layout', 1, True),
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Extension('VK_KHR_sampler_mirror_clamp_to_edge', 1, True),
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@ -30,6 +30,7 @@
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#include "util/mesa-sha1.h"
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#include "util/os_time.h"
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#include "common/gen_l3_config.h"
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#include "common/gen_disasm.h"
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#include "anv_private.h"
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#include "compiler/brw_nir.h"
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#include "anv_nir.h"
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@ -529,6 +530,7 @@ struct anv_pipeline_stage {
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uint32_t num_stats;
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struct brw_compile_stats stats[3];
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char *disasm[3];
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VkPipelineCreationFeedbackEXT feedback;
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@ -1063,6 +1065,77 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler,
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}
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}
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static void
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anv_pipeline_add_executable(struct anv_pipeline *pipeline,
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struct anv_pipeline_stage *stage,
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struct brw_compile_stats *stats,
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uint32_t code_offset)
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{
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char *disasm = NULL;
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if (stage->code &&
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(pipeline->flags &
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VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR)) {
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char *stream_data = NULL;
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size_t stream_size = 0;
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FILE *stream = open_memstream(&stream_data, &stream_size);
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/* Creating this is far cheaper than it looks. It's perfectly fine to
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* do it for every binary.
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*/
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struct gen_disasm *d = gen_disasm_create(&pipeline->device->info);
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gen_disasm_disassemble(d, stage->code, code_offset, stream);
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gen_disasm_destroy(d);
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fclose(stream);
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/* Copy it to a ralloc'd thing */
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disasm = ralloc_size(pipeline->mem_ctx, stream_size + 1);
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memcpy(disasm, stream_data, stream_size);
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disasm[stream_size] = 0;
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free(stream_data);
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}
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pipeline->executables[pipeline->num_executables++] =
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(struct anv_pipeline_executable) {
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.stage = stage->stage,
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.stats = *stats,
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.disasm = disasm,
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};
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}
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static void
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anv_pipeline_add_executables(struct anv_pipeline *pipeline,
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struct anv_pipeline_stage *stage,
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struct anv_shader_bin *bin)
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{
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if (stage->stage == MESA_SHADER_FRAGMENT) {
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/* We pull the prog data and stats out of the anv_shader_bin because
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* the anv_pipeline_stage may not be fully populated if we successfully
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* looked up the shader in a cache.
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*/
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const struct brw_wm_prog_data *wm_prog_data =
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(const struct brw_wm_prog_data *)bin->prog_data;
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struct brw_compile_stats *stats = bin->stats;
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if (wm_prog_data->dispatch_8) {
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anv_pipeline_add_executable(pipeline, stage, stats++, 0);
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}
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if (wm_prog_data->dispatch_16) {
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anv_pipeline_add_executable(pipeline, stage, stats++,
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wm_prog_data->prog_offset_16);
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}
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if (wm_prog_data->dispatch_32) {
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anv_pipeline_add_executable(pipeline, stage, stats++,
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wm_prog_data->prog_offset_32);
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}
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} else {
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anv_pipeline_add_executable(pipeline, stage, bin->stats, 0);
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}
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}
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static VkResult
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anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
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struct anv_pipeline_cache *cache,
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@ -1182,6 +1255,13 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
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VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT;
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}
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/* We found all our shaders in the cache. We're done. */
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for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
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if (!stages[s].entrypoint)
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continue;
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anv_pipeline_add_executables(pipeline, &stages[s],
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pipeline->shaders[s]);
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}
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goto done;
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} else if (found > 0) {
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/* We found some but not all of our shaders. This shouldn't happen
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@ -1335,6 +1415,8 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
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goto fail;
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}
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anv_pipeline_add_executables(pipeline, &stages[s], bin);
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pipeline->shaders[s] = bin;
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ralloc_free(stage_ctx);
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@ -1455,6 +1537,7 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
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&cache_hit);
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}
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void *mem_ctx = ralloc_context(NULL);
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if (bin == NULL) {
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int64_t stage_start = os_time_get_nano();
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@ -1469,8 +1552,6 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
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.set = ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS,
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};
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void *mem_ctx = ralloc_context(NULL);
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stage.nir = anv_pipeline_stage_get_nir(pipeline, cache, mem_ctx, &stage);
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if (stage.nir == NULL) {
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ralloc_free(mem_ctx);
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@ -1511,11 +1592,13 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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}
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ralloc_free(mem_ctx);
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stage.feedback.duration = os_time_get_nano() - stage_start;
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}
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anv_pipeline_add_executables(pipeline, &stage, bin);
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ralloc_free(mem_ctx);
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if (cache_hit) {
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stage.feedback.flags |=
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VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT;
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@ -1823,6 +1906,7 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
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* of various prog_data pointers. Make them NULL by default.
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*/
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memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
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pipeline->num_executables = 0;
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result = anv_pipeline_compile_graphics(pipeline, cache, pCreateInfo);
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if (result != VK_SUCCESS) {
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@ -1909,3 +1993,187 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
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return VK_SUCCESS;
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}
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#define WRITE_STR(field, ...) ({ \
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memset(field, 0, sizeof(field)); \
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UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
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assert(i > 0 && i < sizeof(field)); \
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})
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VkResult anv_GetPipelineExecutablePropertiesKHR(
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VkDevice device,
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const VkPipelineInfoKHR* pPipelineInfo,
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uint32_t* pExecutableCount,
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VkPipelineExecutablePropertiesKHR* pProperties)
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{
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ANV_FROM_HANDLE(anv_pipeline, pipeline, pPipelineInfo->pipeline);
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VK_OUTARRAY_MAKE(out, pProperties, pExecutableCount);
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for (uint32_t i = 0; i < pipeline->num_executables; i++) {
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vk_outarray_append(&out, props) {
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gl_shader_stage stage = pipeline->executables[i].stage;
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props->stages = mesa_to_vk_shader_stage(stage);
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unsigned simd_width = pipeline->executables[i].stats.dispatch_width;
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if (stage == MESA_SHADER_FRAGMENT) {
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WRITE_STR(props->name, "%s%d %s",
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simd_width ? "SIMD" : "vec",
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simd_width ? simd_width : 4,
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_mesa_shader_stage_to_string(stage));
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} else {
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WRITE_STR(props->name, "%s", _mesa_shader_stage_to_string(stage));
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}
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WRITE_STR(props->description, "%s%d %s shader",
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simd_width ? "SIMD" : "vec",
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simd_width ? simd_width : 4,
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_mesa_shader_stage_to_string(stage));
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/* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
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* wants a subgroup size of 1.
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*/
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props->subgroupSize = MAX2(simd_width, 1);
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}
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}
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return vk_outarray_status(&out);
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}
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VkResult anv_GetPipelineExecutableStatisticsKHR(
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VkDevice device,
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const VkPipelineExecutableInfoKHR* pExecutableInfo,
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uint32_t* pStatisticCount,
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VkPipelineExecutableStatisticKHR* pStatistics)
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{
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ANV_FROM_HANDLE(anv_pipeline, pipeline, pExecutableInfo->pipeline);
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VK_OUTARRAY_MAKE(out, pStatistics, pStatisticCount);
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assert(pExecutableInfo->executableIndex < pipeline->num_executables);
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const struct anv_pipeline_executable *exe =
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&pipeline->executables[pExecutableInfo->executableIndex];
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const struct brw_stage_prog_data *prog_data =
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pipeline->shaders[exe->stage]->prog_data;
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vk_outarray_append(&out, stat) {
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WRITE_STR(stat->name, "Instruction Count");
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WRITE_STR(stat->description,
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"Number of GEN instructions in the final generated "
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"shader executable.");
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stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
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stat->value.u64 = exe->stats.instructions;
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}
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vk_outarray_append(&out, stat) {
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WRITE_STR(stat->name, "Loop Count");
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WRITE_STR(stat->description,
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"Number of loops (not unrolled) in the final generated "
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"shader executable.");
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stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
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stat->value.u64 = exe->stats.loops;
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}
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vk_outarray_append(&out, stat) {
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WRITE_STR(stat->name, "Cycle Count");
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WRITE_STR(stat->description,
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"Estimate of the number of EU cycles required to execute "
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"the final generated executable. This is an estimate only "
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"and may vary greatly from actual run-time performance.");
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stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
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stat->value.u64 = exe->stats.cycles;
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}
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vk_outarray_append(&out, stat) {
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WRITE_STR(stat->name, "Spill Count");
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WRITE_STR(stat->description,
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"Number of scratch spill operations. This gives a rough "
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"estimate of the cost incurred due to spilling temporary "
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"values to memory. If this is non-zero, you may want to "
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"adjust your shader to reduce register pressure.");
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stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
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stat->value.u64 = exe->stats.spills;
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}
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vk_outarray_append(&out, stat) {
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WRITE_STR(stat->name, "Fill Count");
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WRITE_STR(stat->description,
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"Number of scratch fill operations. This gives a rough "
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"estimate of the cost incurred due to spilling temporary "
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"values to memory. If this is non-zero, you may want to "
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"adjust your shader to reduce register pressure.");
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stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
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stat->value.u64 = exe->stats.fills;
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}
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vk_outarray_append(&out, stat) {
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WRITE_STR(stat->name, "Scratch Memory Size");
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WRITE_STR(stat->description,
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"Number of bytes of scratch memory required by the "
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"generated shader executable. If this is non-zero, you "
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"may want to adjust your shader to reduce register "
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"pressure.");
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stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
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stat->value.u64 = prog_data->total_scratch;
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}
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if (exe->stage == MESA_SHADER_COMPUTE) {
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vk_outarray_append(&out, stat) {
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WRITE_STR(stat->name, "Workgroup Memory Size");
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WRITE_STR(stat->description,
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"Number of bytes of workgroup shared memory used by this "
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"compute shader including any padding.");
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stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
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stat->value.u64 = prog_data->total_scratch;
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}
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}
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return vk_outarray_status(&out);
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}
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static bool
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write_ir_text(VkPipelineExecutableInternalRepresentationKHR* ir,
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const char *data)
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{
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ir->isText = VK_TRUE;
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size_t data_len = strlen(data) + 1;
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if (ir->pData == NULL) {
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ir->dataSize = data_len;
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return true;
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}
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strncpy(ir->pData, data, ir->dataSize);
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if (ir->dataSize < data_len)
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return false;
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ir->dataSize = data_len;
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return true;
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}
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VkResult anv_GetPipelineExecutableInternalRepresentationsKHR(
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VkDevice device,
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const VkPipelineExecutableInfoKHR* pExecutableInfo,
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uint32_t* pInternalRepresentationCount,
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VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
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{
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ANV_FROM_HANDLE(anv_pipeline, pipeline, pExecutableInfo->pipeline);
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VK_OUTARRAY_MAKE(out, pInternalRepresentations,
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pInternalRepresentationCount);
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bool incomplete_text = false;
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assert(pExecutableInfo->executableIndex < pipeline->num_executables);
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const struct anv_pipeline_executable *exe =
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&pipeline->executables[pExecutableInfo->executableIndex];
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if (exe->disasm) {
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vk_outarray_append(&out, ir) {
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WRITE_STR(ir->name, "GEN Assembly");
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WRITE_STR(ir->description,
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"Final GEN assembly for the generated shader binary");
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if (!write_ir_text(ir, exe->disasm))
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incomplete_text = true;
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}
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}
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return incomplete_text ? VK_INCOMPLETE : vk_outarray_status(&out);
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}
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@ -2794,6 +2794,17 @@ anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
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anv_shader_bin_destroy(device, shader);
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}
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/* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
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#define MAX_PIPELINE_EXECUTABLES 7
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struct anv_pipeline_executable {
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gl_shader_stage stage;
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struct brw_compile_stats stats;
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char *disasm;
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};
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struct anv_pipeline {
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struct anv_device * device;
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struct anv_batch batch;
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@ -2811,6 +2822,9 @@ struct anv_pipeline {
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struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
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uint32_t num_executables;
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struct anv_pipeline_executable executables[MAX_PIPELINE_EXECUTABLES];
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struct {
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const struct gen_l3_config * l3_config;
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uint32_t total_size;
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@ -2233,6 +2233,7 @@ compute_pipeline_create(
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* of various prog_data pointers. Make them NULL by default.
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*/
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memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
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pipeline->num_executables = 0;
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pipeline->needs_data_cache = false;
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