amd: add Dimgrey Cavefish support
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6820>
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@ -99,6 +99,7 @@
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#define AMDGPU_NAVI14_RANGE 0x14, 0x28
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#define AMDGPU_NAVI14_RANGE 0x14, 0x28
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#define AMDGPU_SIENNA_CICHLID_RANGE 0x28, 0x32
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#define AMDGPU_SIENNA_CICHLID_RANGE 0x28, 0x32
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#define AMDGPU_NAVY_FLOUNDER_RANGE 0x32, 0x3C
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#define AMDGPU_NAVY_FLOUNDER_RANGE 0x32, 0x3C
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#define AMDGPU_DIMGREY_CAVEFISH_RANGE 0x3C, 0x46
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#define AMDGPU_EXPAND_FIX(x) x
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#define AMDGPU_EXPAND_FIX(x) x
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#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
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#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
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@ -148,5 +149,6 @@
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#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14)
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#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14)
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#define ASICREV_IS_SIENNA_CICHLID(r) ASICREV_IS(r, SIENNA_CICHLID)
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#define ASICREV_IS_SIENNA_CICHLID(r) ASICREV_IS(r, SIENNA_CICHLID)
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#define ASICREV_IS_NAVY_FLOUNDER(r) ASICREV_IS(r, NAVY_FLOUNDER)
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#define ASICREV_IS_NAVY_FLOUNDER(r) ASICREV_IS(r, NAVY_FLOUNDER)
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#define ASICREV_IS_DIMGREY_CAVEFISH(r) ASICREV_IS(r, DIMGREY_CAVEFISH)
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#endif // _AMDGPU_ASIC_ADDR_H
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#endif // _AMDGPU_ASIC_ADDR_H
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@ -933,6 +933,12 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
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m_settings.supportRbPlus = 1;
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m_settings.supportRbPlus = 1;
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m_settings.dccUnsup3DSwDis = 0;
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m_settings.dccUnsup3DSwDis = 0;
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}
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}
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if (ASICREV_IS_DIMGREY_CAVEFISH(chipRevision))
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{
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m_settings.supportRbPlus = 1;
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m_settings.dccUnsup3DSwDis = 0;
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}
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break;
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break;
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default:
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default:
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ADDR_ASSERT(!"Unknown chip family");
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ADDR_ASSERT(!"Unknown chip family");
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@ -400,6 +400,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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identify_chip(NAVI14);
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identify_chip(NAVI14);
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identify_chip(SIENNA_CICHLID);
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identify_chip(SIENNA_CICHLID);
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identify_chip(NAVY_FLOUNDER);
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identify_chip(NAVY_FLOUNDER);
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identify_chip(DIMGREY_CAVEFISH);
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break;
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break;
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}
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}
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@ -706,6 +707,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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case CHIP_NAVI12:
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case CHIP_NAVI12:
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case CHIP_SIENNA_CICHLID:
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_DIMGREY_CAVEFISH:
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pc_lines = 1024;
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pc_lines = 1024;
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break;
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break;
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case CHIP_NAVI14:
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case CHIP_NAVI14:
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@ -105,6 +105,7 @@ enum radeon_family
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CHIP_NAVI14,
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CHIP_NAVI14,
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CHIP_SIENNA_CICHLID,
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CHIP_SIENNA_CICHLID,
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CHIP_NAVY_FLOUNDER,
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CHIP_NAVY_FLOUNDER,
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CHIP_DIMGREY_CAVEFISH,
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CHIP_LAST,
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CHIP_LAST,
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};
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};
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@ -176,6 +176,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
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return "gfx1012";
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return "gfx1012";
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case CHIP_SIENNA_CICHLID:
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_DIMGREY_CAVEFISH:
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return "gfx1030";
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return "gfx1030";
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default:
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default:
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return "";
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return "";
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@ -1614,6 +1614,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
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case CHIP_ARCTURUS:
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case CHIP_ARCTURUS:
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case CHIP_SIENNA_CICHLID:
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_DIMGREY_CAVEFISH:
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dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
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dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
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dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
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dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
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dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
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dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
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