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radeon/llvm: Fix build for updated LLVM 3.1 release branch

This commit is contained in:
Tom Stellard 2012-05-01 16:40:53 -04:00
parent 07f5dabc01
commit d742d812d8
2 changed files with 18 additions and 18 deletions
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26
src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
View File

@ -112,31 +112,31 @@ AMDGPUPassConfig::addPreISel()
{
const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
PM.add(createR600KernelParametersPass(
PM->add(createR600KernelParametersPass(
getAMDGPUTargetMachine().getTargetData()));
}
return false;
}
bool AMDGPUPassConfig::addInstSelector() {
PM.add(createAMDILPeepholeOpt(*TM));
PM.add(createAMDILISelDag(getAMDGPUTargetMachine()));
PM->add(createAMDILPeepholeOpt(*TM));
PM->add(createAMDILISelDag(getAMDGPUTargetMachine()));
return false;
}
bool AMDGPUPassConfig::addPreRegAlloc() {
const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
PM.add(createAMDGPUReorderPreloadInstructionsPass(*TM));
PM->add(createAMDGPUReorderPreloadInstructionsPass(*TM));
if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
PM.add(createR600LowerShaderInstructionsPass(*TM));
PM.add(createR600LowerInstructionsPass(*TM));
PM->add(createR600LowerShaderInstructionsPass(*TM));
PM->add(createR600LowerInstructionsPass(*TM));
} else {
PM.add(createSILowerShaderInstructionsPass(*TM));
PM.add(createSIAssignInterpRegsPass(*TM));
PM->add(createSILowerShaderInstructionsPass(*TM));
PM->add(createSIAssignInterpRegsPass(*TM));
}
PM.add(createAMDGPULowerInstructionsPass(*TM));
PM.add(createAMDGPUConvertToISAPass(*TM));
PM->add(createAMDGPULowerInstructionsPass(*TM));
PM->add(createAMDGPUConvertToISAPass(*TM));
return false;
}
@ -150,10 +150,10 @@ bool AMDGPUPassConfig::addPreSched2() {
bool AMDGPUPassConfig::addPreEmitPass() {
const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
PM.add(createAMDILCFGPreparationPass(*TM));
PM.add(createAMDILCFGStructurizerPass(*TM));
PM->add(createAMDILCFGPreparationPass(*TM));
PM->add(createAMDILCFGStructurizerPass(*TM));
if (ST.device()->getGeneration() == AMDILDeviceInfo::HD7XXX) {
PM.add(createSIPropagateImmReadsPass(*TM));
PM->add(createSIPropagateImmReadsPass(*TM));
}
return false;

10
src/gallium/drivers/radeon/AMDILTargetMachine.cpp
View File

@ -150,8 +150,8 @@ bool AMDILPassConfig::addPreISel()
bool AMDILPassConfig::addInstSelector()
{
PM.add(createAMDILPeepholeOpt(*TM));
PM.add(createAMDILISelDag(getAMDILTargetMachine()));
PM->add(createAMDILPeepholeOpt(*TM));
PM->add(createAMDILISelDag(getAMDILTargetMachine()));
return false;
}
@ -162,7 +162,7 @@ bool AMDILPassConfig::addPreRegAlloc()
llvm::RegisterScheduler::setDefault(&llvm::createSourceListDAGScheduler);
}
PM.add(createAMDILMachinePeephole(*TM));
PM->add(createAMDILMachinePeephole(*TM));
return false;
}
@ -175,8 +175,8 @@ bool AMDILPassConfig::addPostRegAlloc() {
/// true if -print-machineinstrs should print out the code after the passes.
bool AMDILPassConfig::addPreEmitPass()
{
PM.add(createAMDILCFGPreparationPass(*TM));
PM.add(createAMDILCFGStructurizerPass(*TM));
PM->add(createAMDILCFGPreparationPass(*TM));
PM->add(createAMDILCFGStructurizerPass(*TM));
return true;
}