i965/fs: Define new shader opcode to set rounding modes
Although it is possible to emit them directly as AND/OR on brw_fs_nir, having a specific opcode makes it easier to remove duplicate settings later. v2: (Curro) - Set thread control to 'switch' when using the control register - Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate with the rounding mode. - Avoid magic numbers setting rounding mode field at control register. v3: (Curro) - Remove redundant and add missing whitespace lines. - Match printing instruction to IR opcode "rnd_mode" v4: (Topi Pohjolainen) - Fix code style. Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com> Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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@ -510,6 +510,10 @@ brw_broadcast(struct brw_codegen *p,
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struct brw_reg src,
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struct brw_reg src,
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struct brw_reg idx);
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struct brw_reg idx);
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void
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brw_rounding_mode(struct brw_codegen *p,
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enum brw_rnd_mode mode);
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/***********************************************************************
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/***********************************************************************
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* brw_eu_util.c:
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* brw_eu_util.c:
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*/
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*/
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@ -400,6 +400,8 @@ enum opcode {
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SHADER_OPCODE_TYPED_SURFACE_WRITE,
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SHADER_OPCODE_TYPED_SURFACE_WRITE,
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SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
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SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
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SHADER_OPCODE_RND_MODE,
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SHADER_OPCODE_MEMORY_FENCE,
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SHADER_OPCODE_MEMORY_FENCE,
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SHADER_OPCODE_GEN4_SCRATCH_READ,
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SHADER_OPCODE_GEN4_SCRATCH_READ,
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@ -1238,4 +1240,18 @@ enum brw_message_target {
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/* R0 */
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/* R0 */
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# define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
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# define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
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/* CR0.0[5:4] Floating-Point Rounding Modes
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* Skylake PRM, Volume 7 Part 1, "Control Register", page 756
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*/
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#define BRW_CR0_RND_MODE_MASK 0x30
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#define BRW_CR0_RND_MODE_SHIFT 4
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enum PACKED brw_rnd_mode {
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BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
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BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
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BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
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BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
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};
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#endif /* BRW_EU_DEFINES_H */
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#endif /* BRW_EU_DEFINES_H */
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@ -3589,3 +3589,36 @@ brw_WAIT(struct brw_codegen *p)
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brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
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brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
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brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
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brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
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}
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}
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/**
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* Changes the floating point rounding mode updating the control register
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* field defined at cr0.0[5-6] bits. This function supports the changes to
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* RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise operations.
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* Only RTNE and RTZ rounding are enabled at nir.
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*/
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void
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brw_rounding_mode(struct brw_codegen *p,
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enum brw_rnd_mode mode)
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{
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const unsigned bits = mode << BRW_CR0_RND_MODE_SHIFT;
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if (bits != BRW_CR0_RND_MODE_MASK) {
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brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
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brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
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/* From the Skylake PRM, Volume 7, page 760:
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* "Implementation Restriction on Register Access: When the control
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* register is used as an explicit source and/or destination, hardware
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* does not ensure execution pipeline coherency. Software must set the
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* thread control field to ‘switch’ for an instruction that uses
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* control register as an explicit operand."
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*/
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brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
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}
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if (bits) {
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brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
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brw_imm_ud(bits));
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brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
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}
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}
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@ -2176,6 +2176,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
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brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
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break;
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break;
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case SHADER_OPCODE_RND_MODE:
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assert(src[0].file == BRW_IMMEDIATE_VALUE);
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brw_rounding_mode(p, (brw_rnd_mode) src[0].d);
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break;
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default:
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default:
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unreachable("Unsupported opcode");
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unreachable("Unsupported opcode");
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@ -482,6 +482,9 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
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return "tes_add_indirect_urb_offset";
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return "tes_add_indirect_urb_offset";
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case TES_OPCODE_GET_PRIMITIVE_ID:
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case TES_OPCODE_GET_PRIMITIVE_ID:
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return "tes_get_primitive_id";
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return "tes_get_primitive_id";
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case SHADER_OPCODE_RND_MODE:
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return "rnd_mode";
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}
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}
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unreachable("not reached");
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unreachable("not reached");
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@ -974,6 +977,7 @@ backend_instruction::has_side_effects() const
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case SHADER_OPCODE_BARRIER:
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case SHADER_OPCODE_BARRIER:
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case TCS_OPCODE_URB_WRITE:
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case TCS_OPCODE_URB_WRITE:
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case TCS_OPCODE_RELEASE_INPUT:
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case TCS_OPCODE_RELEASE_INPUT:
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case SHADER_OPCODE_RND_MODE:
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return true;
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return true;
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default:
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default:
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return eot;
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return eot;
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