anv/cmd_buffer: Take an address in emit_lrm
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
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e1ab834557
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@ -33,12 +33,11 @@
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#include "genxml/genX_pack.h"
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static void
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emit_lrm(struct anv_batch *batch,
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uint32_t reg, struct anv_bo *bo, uint32_t offset)
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emit_lrm(struct anv_batch *batch, uint32_t reg, struct anv_address addr)
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{
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anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
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lrm.RegisterAddress = reg;
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lrm.MemoryAddress = (struct anv_address) { bo, offset };
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lrm.MemoryAddress = addr;
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}
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}
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@ -2868,30 +2867,30 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
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{
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struct anv_batch *batch = &cmd_buffer->batch;
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emit_lrm(batch, GEN7_3DPRIM_VERTEX_COUNT, addr.bo, addr.offset);
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emit_lrm(batch, GEN7_3DPRIM_VERTEX_COUNT, anv_address_add(addr, 0));
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unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass);
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if (view_count > 1) {
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#if GEN_IS_HASWELL || GEN_GEN >= 8
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emit_lrm(batch, CS_GPR(0), addr.bo, addr.offset + 4);
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emit_lrm(batch, CS_GPR(0), anv_address_add(addr, 4));
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emit_mul_gpr0(batch, view_count);
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emit_lrr(batch, GEN7_3DPRIM_INSTANCE_COUNT, CS_GPR(0));
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#else
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anv_finishme("Multiview + indirect draw requires MI_MATH; "
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"MI_MATH is not supported on Ivy Bridge");
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emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, addr.bo, addr.offset + 4);
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emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, anv_address_add(addr, 4));
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#endif
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} else {
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emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, addr.bo, addr.offset + 4);
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emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, anv_address_add(addr, 4));
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}
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emit_lrm(batch, GEN7_3DPRIM_START_VERTEX, addr.bo, addr.offset + 8);
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emit_lrm(batch, GEN7_3DPRIM_START_VERTEX, anv_address_add(addr, 8));
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if (indexed) {
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emit_lrm(batch, GEN7_3DPRIM_BASE_VERTEX, addr.bo, addr.offset + 12);
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emit_lrm(batch, GEN7_3DPRIM_START_INSTANCE, addr.bo, addr.offset + 16);
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emit_lrm(batch, GEN7_3DPRIM_BASE_VERTEX, anv_address_add(addr, 12));
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emit_lrm(batch, GEN7_3DPRIM_START_INSTANCE, anv_address_add(addr, 16));
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} else {
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emit_lrm(batch, GEN7_3DPRIM_START_INSTANCE, addr.bo, addr.offset + 12);
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emit_lrm(batch, GEN7_3DPRIM_START_INSTANCE, anv_address_add(addr, 12));
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emit_lri(batch, GEN7_3DPRIM_BASE_VERTEX, 0);
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}
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}
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@ -3225,9 +3224,9 @@ void genX(CmdDispatchIndirect)(
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genX(cmd_buffer_flush_compute_state)(cmd_buffer);
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emit_lrm(batch, GPGPU_DISPATCHDIMX, addr.bo, addr.offset);
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emit_lrm(batch, GPGPU_DISPATCHDIMY, addr.bo, addr.offset + 4);
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emit_lrm(batch, GPGPU_DISPATCHDIMZ, addr.bo, addr.offset + 8);
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emit_lrm(batch, GPGPU_DISPATCHDIMX, anv_address_add(addr, 0));
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emit_lrm(batch, GPGPU_DISPATCHDIMY, anv_address_add(addr, 4));
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emit_lrm(batch, GPGPU_DISPATCHDIMZ, anv_address_add(addr, 8));
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#if GEN_GEN <= 7
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/* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
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@ -3236,7 +3235,7 @@ void genX(CmdDispatchIndirect)(
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emit_lri(batch, MI_PREDICATE_SRC1 + 4, 0);
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/* Load compute_dispatch_indirect_x_size into SRC0 */
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emit_lrm(batch, MI_PREDICATE_SRC0, addr.bo, addr.offset + 0);
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emit_lrm(batch, MI_PREDICATE_SRC0, anv_address_add(addr, 0));
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/* predicate = (compute_dispatch_indirect_x_size == 0); */
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anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
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@ -3246,7 +3245,7 @@ void genX(CmdDispatchIndirect)(
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}
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/* Load compute_dispatch_indirect_y_size into SRC0 */
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emit_lrm(batch, MI_PREDICATE_SRC0, addr.bo, addr.offset + 4);
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emit_lrm(batch, MI_PREDICATE_SRC0, anv_address_add(addr, 4));
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/* predicate |= (compute_dispatch_indirect_y_size == 0); */
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anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
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@ -3256,7 +3255,7 @@ void genX(CmdDispatchIndirect)(
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}
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/* Load compute_dispatch_indirect_z_size into SRC0 */
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emit_lrm(batch, MI_PREDICATE_SRC0, addr.bo, addr.offset + 8);
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emit_lrm(batch, MI_PREDICATE_SRC0, anv_address_add(addr, 8));
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/* predicate |= (compute_dispatch_indirect_z_size == 0); */
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anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
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