intel/inst: Indent some code
We're about to add some more if cases so let's have the giant re-indent in it's own patch to make review easier. Acked-by: Iago Toral Quiroga <itoral@igalia.com>
This commit is contained in:
Jason Ekstrand
Jason Ekstrand
parent
d96969120d
commit
d6a6e10390
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@ -96,46 +96,48 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
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gen7_convert_mrf_to_grf(p, &dest);
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brw_inst_set_dst_file_type(devinfo, inst, dest.file, dest.type);
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brw_inst_set_dst_address_mode(devinfo, inst, dest.address_mode);
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{
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brw_inst_set_dst_file_type(devinfo, inst, dest.file, dest.type);
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brw_inst_set_dst_address_mode(devinfo, inst, dest.address_mode);
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if (dest.address_mode == BRW_ADDRESS_DIRECT) {
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brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr);
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if (dest.address_mode == BRW_ADDRESS_DIRECT) {
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brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr);
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr);
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if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
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dest.hstride = BRW_HORIZONTAL_STRIDE_1;
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brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
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} else {
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brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
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brw_inst_set_da16_writemask(devinfo, inst, dest.writemask);
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if (dest.file == BRW_GENERAL_REGISTER_FILE ||
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dest.file == BRW_MESSAGE_REGISTER_FILE) {
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assert(dest.writemask != 0);
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr);
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if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
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dest.hstride = BRW_HORIZONTAL_STRIDE_1;
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brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
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} else {
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brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
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brw_inst_set_da16_writemask(devinfo, inst, dest.writemask);
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if (dest.file == BRW_GENERAL_REGISTER_FILE ||
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dest.file == BRW_MESSAGE_REGISTER_FILE) {
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assert(dest.writemask != 0);
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}
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/* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
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* Although Dst.HorzStride is a don't care for Align16, HW needs
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* this to be programmed as "01".
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*/
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brw_inst_set_dst_hstride(devinfo, inst, 1);
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}
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/* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
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* Although Dst.HorzStride is a don't care for Align16, HW needs
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* this to be programmed as "01".
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*/
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brw_inst_set_dst_hstride(devinfo, inst, 1);
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}
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} else {
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brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr);
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/* These are different sizes in align1 vs align16:
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*/
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_dst_ia1_addr_imm(devinfo, inst,
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dest.indirect_offset);
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if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
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dest.hstride = BRW_HORIZONTAL_STRIDE_1;
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brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
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} else {
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brw_inst_set_dst_ia16_addr_imm(devinfo, inst,
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dest.indirect_offset);
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/* even ignored in da16, still need to set as '01' */
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brw_inst_set_dst_hstride(devinfo, inst, 1);
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brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr);
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/* These are different sizes in align1 vs align16:
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*/
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_dst_ia1_addr_imm(devinfo, inst,
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dest.indirect_offset);
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if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
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dest.hstride = BRW_HORIZONTAL_STRIDE_1;
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brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
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} else {
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brw_inst_set_dst_ia16_addr_imm(devinfo, inst,
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dest.indirect_offset);
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/* even ignored in da16, still need to set as '01' */
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brw_inst_set_dst_hstride(devinfo, inst, 1);
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}
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}
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}
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@ -186,84 +188,86 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
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assert(reg.address_mode == BRW_ADDRESS_DIRECT);
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}
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brw_inst_set_src0_file_type(devinfo, inst, reg.file, reg.type);
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brw_inst_set_src0_abs(devinfo, inst, reg.abs);
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brw_inst_set_src0_negate(devinfo, inst, reg.negate);
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brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode);
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{
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brw_inst_set_src0_file_type(devinfo, inst, reg.file, reg.type);
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brw_inst_set_src0_abs(devinfo, inst, reg.abs);
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brw_inst_set_src0_negate(devinfo, inst, reg.negate);
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brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode);
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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if (reg.type == BRW_REGISTER_TYPE_DF ||
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brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM)
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brw_inst_set_imm_df(devinfo, inst, reg.df);
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else if (reg.type == BRW_REGISTER_TYPE_UQ ||
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reg.type == BRW_REGISTER_TYPE_Q)
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brw_inst_set_imm_uq(devinfo, inst, reg.u64);
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else
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brw_inst_set_imm_ud(devinfo, inst, reg.ud);
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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if (reg.type == BRW_REGISTER_TYPE_DF ||
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brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM)
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brw_inst_set_imm_df(devinfo, inst, reg.df);
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else if (reg.type == BRW_REGISTER_TYPE_UQ ||
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reg.type == BRW_REGISTER_TYPE_Q)
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brw_inst_set_imm_uq(devinfo, inst, reg.u64);
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else
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brw_inst_set_imm_ud(devinfo, inst, reg.ud);
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if (type_sz(reg.type) < 8) {
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brw_inst_set_src1_reg_file(devinfo, inst,
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BRW_ARCHITECTURE_REGISTER_FILE);
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brw_inst_set_src1_reg_hw_type(devinfo, inst,
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brw_inst_src0_reg_hw_type(devinfo, inst));
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}
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} else {
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if (reg.address_mode == BRW_ADDRESS_DIRECT) {
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brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr);
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr);
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} else {
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brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
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}
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if (type_sz(reg.type) < 8) {
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brw_inst_set_src1_reg_file(devinfo, inst,
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BRW_ARCHITECTURE_REGISTER_FILE);
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brw_inst_set_src1_reg_hw_type(devinfo, inst,
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brw_inst_src0_reg_hw_type(devinfo, inst));
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}
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} else {
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brw_inst_set_src0_ia_subreg_nr(devinfo, inst, reg.subnr);
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset);
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} else {
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brw_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.indirect_offset);
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}
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}
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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if (reg.width == BRW_WIDTH_1 &&
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brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) {
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brw_inst_set_src0_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0);
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brw_inst_set_src0_width(devinfo, inst, BRW_WIDTH_1);
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brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
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} else {
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brw_inst_set_src0_hstride(devinfo, inst, reg.hstride);
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brw_inst_set_src0_width(devinfo, inst, reg.width);
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brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
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}
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} else {
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brw_inst_set_src0_da16_swiz_x(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X));
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brw_inst_set_src0_da16_swiz_y(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y));
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brw_inst_set_src0_da16_swiz_z(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z));
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brw_inst_set_src0_da16_swiz_w(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
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if (reg.vstride == BRW_VERTICAL_STRIDE_8) {
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/* This is an oddity of the fact we're using the same
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* descriptions for registers in align_16 as align_1:
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*/
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brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
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} else if (devinfo->gen == 7 && !devinfo->is_haswell &&
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reg.type == BRW_REGISTER_TYPE_DF &&
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reg.vstride == BRW_VERTICAL_STRIDE_2) {
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/* From SNB PRM:
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*
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* "For Align16 access mode, only encodings of 0000 and 0011
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* are allowed. Other codes are reserved."
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*
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* Presumably the DevSNB behavior applies to IVB as well.
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*/
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brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
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if (reg.address_mode == BRW_ADDRESS_DIRECT) {
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brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr);
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr);
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} else {
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brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
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}
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} else {
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brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
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brw_inst_set_src0_ia_subreg_nr(devinfo, inst, reg.subnr);
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset);
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} else {
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brw_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.indirect_offset);
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}
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}
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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if (reg.width == BRW_WIDTH_1 &&
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brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) {
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brw_inst_set_src0_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0);
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brw_inst_set_src0_width(devinfo, inst, BRW_WIDTH_1);
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brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
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} else {
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brw_inst_set_src0_hstride(devinfo, inst, reg.hstride);
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brw_inst_set_src0_width(devinfo, inst, reg.width);
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brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
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}
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} else {
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brw_inst_set_src0_da16_swiz_x(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X));
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brw_inst_set_src0_da16_swiz_y(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y));
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brw_inst_set_src0_da16_swiz_z(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z));
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brw_inst_set_src0_da16_swiz_w(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
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if (reg.vstride == BRW_VERTICAL_STRIDE_8) {
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/* This is an oddity of the fact we're using the same
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* descriptions for registers in align_16 as align_1:
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*/
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brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
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} else if (devinfo->gen == 7 && !devinfo->is_haswell &&
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reg.type == BRW_REGISTER_TYPE_DF &&
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reg.vstride == BRW_VERTICAL_STRIDE_2) {
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/* From SNB PRM:
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*
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* "For Align16 access mode, only encodings of 0000 and 0011
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* are allowed. Other codes are reserved."
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*
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* Presumably the DevSNB behavior applies to IVB as well.
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*/
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brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
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} else {
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brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
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}
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}
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}
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}
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@ -278,82 +282,84 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
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if (reg.file == BRW_GENERAL_REGISTER_FILE)
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assert(reg.nr < 128);
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/* From the IVB PRM Vol. 4, Pt. 3, Section 3.3.3.5:
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*
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* "Accumulator registers may be accessed explicitly as src0
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* operands only."
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*/
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assert(reg.file != BRW_ARCHITECTURE_REGISTER_FILE ||
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reg.nr != BRW_ARF_ACCUMULATOR);
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gen7_convert_mrf_to_grf(p, ®);
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assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
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brw_inst_set_src1_file_type(devinfo, inst, reg.file, reg.type);
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brw_inst_set_src1_abs(devinfo, inst, reg.abs);
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brw_inst_set_src1_negate(devinfo, inst, reg.negate);
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/* Only src1 can be immediate in two-argument instructions.
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*/
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assert(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE);
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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/* two-argument instructions can only use 32-bit immediates */
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assert(type_sz(reg.type) < 8);
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brw_inst_set_imm_ud(devinfo, inst, reg.ud);
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} else {
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/* This is a hardware restriction, which may or may not be lifted
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* in the future:
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{
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/* From the IVB PRM Vol. 4, Pt. 3, Section 3.3.3.5:
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*
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* "Accumulator registers may be accessed explicitly as src0
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* operands only."
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*/
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assert (reg.address_mode == BRW_ADDRESS_DIRECT);
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/* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
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assert(reg.file != BRW_ARCHITECTURE_REGISTER_FILE ||
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reg.nr != BRW_ARF_ACCUMULATOR);
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brw_inst_set_src1_da_reg_nr(devinfo, inst, reg.nr);
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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brw_inst_set_src1_da1_subreg_nr(devinfo, inst, reg.subnr);
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gen7_convert_mrf_to_grf(p, ®);
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assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
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brw_inst_set_src1_file_type(devinfo, inst, reg.file, reg.type);
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brw_inst_set_src1_abs(devinfo, inst, reg.abs);
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brw_inst_set_src1_negate(devinfo, inst, reg.negate);
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/* Only src1 can be immediate in two-argument instructions.
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*/
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assert(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE);
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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/* two-argument instructions can only use 32-bit immediates */
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assert(type_sz(reg.type) < 8);
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brw_inst_set_imm_ud(devinfo, inst, reg.ud);
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} else {
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brw_inst_set_src1_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
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}
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/* This is a hardware restriction, which may or may not be lifted
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* in the future:
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*/
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assert (reg.address_mode == BRW_ADDRESS_DIRECT);
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/* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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if (reg.width == BRW_WIDTH_1 &&
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brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) {
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brw_inst_set_src1_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0);
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brw_inst_set_src1_width(devinfo, inst, BRW_WIDTH_1);
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brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
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} else {
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brw_inst_set_src1_hstride(devinfo, inst, reg.hstride);
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brw_inst_set_src1_width(devinfo, inst, reg.width);
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brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
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}
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} else {
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brw_inst_set_src1_da16_swiz_x(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X));
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brw_inst_set_src1_da16_swiz_y(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y));
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brw_inst_set_src1_da16_swiz_z(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z));
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brw_inst_set_src1_da16_swiz_w(devinfo, inst,
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BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
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if (reg.vstride == BRW_VERTICAL_STRIDE_8) {
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/* This is an oddity of the fact we're using the same
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* descriptions for registers in align_16 as align_1:
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*/
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brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
|
||||
} else if (devinfo->gen == 7 && !devinfo->is_haswell &&
|
||||
reg.type == BRW_REGISTER_TYPE_DF &&
|
||||
reg.vstride == BRW_VERTICAL_STRIDE_2) {
|
||||
/* From SNB PRM:
|
||||
*
|
||||
* "For Align16 access mode, only encodings of 0000 and 0011
|
||||
* are allowed. Other codes are reserved."
|
||||
*
|
||||
* Presumably the DevSNB behavior applies to IVB as well.
|
||||
*/
|
||||
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_da_reg_nr(devinfo, inst, reg.nr);
|
||||
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
|
||||
brw_inst_set_src1_da1_subreg_nr(devinfo, inst, reg.subnr);
|
||||
} else {
|
||||
brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
|
||||
brw_inst_set_src1_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
|
||||
}
|
||||
|
||||
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
|
||||
if (reg.width == BRW_WIDTH_1 &&
|
||||
brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) {
|
||||
brw_inst_set_src1_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0);
|
||||
brw_inst_set_src1_width(devinfo, inst, BRW_WIDTH_1);
|
||||
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
|
||||
} else {
|
||||
brw_inst_set_src1_hstride(devinfo, inst, reg.hstride);
|
||||
brw_inst_set_src1_width(devinfo, inst, reg.width);
|
||||
brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
|
||||
}
|
||||
} else {
|
||||
brw_inst_set_src1_da16_swiz_x(devinfo, inst,
|
||||
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X));
|
||||
brw_inst_set_src1_da16_swiz_y(devinfo, inst,
|
||||
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y));
|
||||
brw_inst_set_src1_da16_swiz_z(devinfo, inst,
|
||||
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z));
|
||||
brw_inst_set_src1_da16_swiz_w(devinfo, inst,
|
||||
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
|
||||
|
||||
if (reg.vstride == BRW_VERTICAL_STRIDE_8) {
|
||||
/* This is an oddity of the fact we're using the same
|
||||
* descriptions for registers in align_16 as align_1:
|
||||
*/
|
||||
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
|
||||
} else if (devinfo->gen == 7 && !devinfo->is_haswell &&
|
||||
reg.type == BRW_REGISTER_TYPE_DF &&
|
||||
reg.vstride == BRW_VERTICAL_STRIDE_2) {
|
||||
/* From SNB PRM:
|
||||
*
|
||||
* "For Align16 access mode, only encodings of 0000 and 0011
|
||||
* are allowed. Other codes are reserved."
|
||||
*
|
||||
* Presumably the DevSNB behavior applies to IVB as well.
|
||||
*/
|
||||
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
|
||||
} else {
|
||||
brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue