ac/nir: don't trash L1 caches for store operations with writeonly memory
Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -1465,7 +1465,8 @@ static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueR
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static unsigned get_cache_policy(struct ac_nir_context *ctx,
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enum gl_access_qualifier access,
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bool may_store_unaligned)
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bool may_store_unaligned,
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bool writeonly_memory)
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{
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unsigned cache_policy = 0;
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@ -1474,6 +1475,11 @@ static unsigned get_cache_policy(struct ac_nir_context *ctx,
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* get unaligned stores is through shader images.
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*/
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if (((may_store_unaligned && ctx->ac.chip_class == SI) ||
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/* If this is write-only, don't keep data in L1 to prevent
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* evicting L1 cache lines that may be needed by other
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* instructions.
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*/
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writeonly_memory ||
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access & (ACCESS_COHERENT | ACCESS_VOLATILE))) {
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cache_policy |= ac_glc;
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}
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@ -1489,7 +1495,8 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
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int elem_size_bytes = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 8;
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unsigned writemask = nir_intrinsic_write_mask(instr);
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enum gl_access_qualifier access = nir_intrinsic_access(instr);
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unsigned cache_policy = get_cache_policy(ctx, access, false);
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bool writeonly_memory = access & ACCESS_NON_READABLE;
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unsigned cache_policy = get_cache_policy(ctx, access, false, writeonly_memory);
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LLVMValueRef glc = (cache_policy & ac_glc) ? ctx->ac.i1true : ctx->ac.i1false;
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LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi,
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@ -1646,7 +1653,7 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
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int elem_size_bytes = instr->dest.ssa.bit_size / 8;
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int num_components = instr->num_components;
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enum gl_access_qualifier access = nir_intrinsic_access(instr);
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unsigned cache_policy = get_cache_policy(ctx, access, false);
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unsigned cache_policy = get_cache_policy(ctx, access, false, false);
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LLVMValueRef glc = (cache_policy & ac_glc) ? ctx->ac.i1true : ctx->ac.i1false;
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LLVMValueRef offset = get_src(ctx, instr->src[1]);
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@ -2359,7 +2366,8 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
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type = glsl_without_array(type);
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args.cache_policy = get_cache_policy(ctx, var->data.image.access, false);
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args.cache_policy =
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get_cache_policy(ctx, var->data.image.access, false, false);
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const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
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if (dim == GLSL_SAMPLER_DIM_BUF) {
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@ -2401,9 +2409,11 @@ static void visit_image_store(struct ac_nir_context *ctx,
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const nir_variable *var = get_image_variable(instr);
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const struct glsl_type *type = glsl_without_array(var->type);
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const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
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bool writeonly_memory = var->data.image.access & ACCESS_NON_READABLE;
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struct ac_image_args args = {};
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args.cache_policy = get_cache_policy(ctx, var->data.image.access, true);
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args.cache_policy = get_cache_policy(ctx, var->data.image.access, true,
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writeonly_memory);
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if (dim == GLSL_SAMPLER_DIM_BUF) {
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char name[48];
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