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intel/compiler: Adjust TCS instance-id for dg2+ 

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14385>
This commit is contained in:
Jordan Justen 2020-07-13 22:24:19 -07:00
parent 9f58275f98
commit d57b10ab98
1 changed files with 10 additions and 3 deletions
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13
src/intel/compiler/brw_fs.cpp
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@ -8816,12 +8816,19 @@ fs_visitor::set_tcs_invocation_id()
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
const bool dg2_plus =
devinfo->ver > 12 || intel_device_info_is_dg2(devinfo);
const unsigned instance_id_mask =
devinfo->ver >= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
dg2_plus ? INTEL_MASK(7, 0) :
(devinfo->ver >= 11) ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
const unsigned instance_id_shift =
devinfo->ver >= 11 ? 16 : 17;
dg2_plus ? 0 : (devinfo->ver >= 11) ? 16 : 17;
/* Get instance number from g0.2 bits 22:16 or 23:17 */
/* Get instance number from g0.2 bits:
* * 7:0 on DG2+
* * 22:16 on gfx11+
* * 23:17 otherwise
*/
fs_reg t = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.AND(t, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(instance_id_mask));