i965: Drop trailing whitespace from files shared with intel-gpu-tools.
Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
parent
3be333ed30
commit
d542c45c75
|
@ -2,7 +2,7 @@
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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develop this 3D driver.
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|
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
|
@ -10,11 +10,11 @@
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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@ -22,13 +22,13 @@
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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*/
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#include "brw_context.h"
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#include "brw_defines.h"
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@ -76,7 +76,7 @@ void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
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}
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p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
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}
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}
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}
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void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
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@ -163,7 +163,7 @@ void brw_push_insn_state( struct brw_compile *p )
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assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
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memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
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p->compressed_stack[p->current - p->stack] = p->compressed;
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p->current++;
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p->current++;
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}
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void brw_pop_insn_state( struct brw_compile *p )
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@ -201,7 +201,7 @@ brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
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brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
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brw_set_saturate(p, 0);
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brw_set_compression_control(p, BRW_COMPRESSION_NONE);
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brw_set_predicate_control_flag_value(p, 0xff);
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brw_set_predicate_control_flag_value(p, 0xff);
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/* Set up control flow stack */
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p->if_stack_depth = 0;
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|
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@ -2,7 +2,7 @@
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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develop this 3D driver.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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|
@ -10,11 +10,11 @@
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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|
||||
|
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The above copyright notice and this permission notice (including the
|
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next paragraph) shall be included in all copies or substantial
|
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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@ -22,13 +22,13 @@
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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*/
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#ifndef BRW_EU_H
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#define BRW_EU_H
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@ -320,7 +320,7 @@ void brw_shader_time_add(struct brw_compile *p,
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/* If/else/endif. Works by manipulating the execution flags on each
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* channel.
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*/
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struct brw_instruction *brw_IF(struct brw_compile *p,
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struct brw_instruction *brw_IF(struct brw_compile *p,
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GLuint execute_size);
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struct brw_instruction *gen6_IF(struct brw_compile *p, uint32_t conditional,
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struct brw_reg src0, struct brw_reg src1);
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@ -375,7 +375,7 @@ brw_untyped_surface_read(struct brw_compile *p,
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GLuint msg_length,
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GLuint response_length);
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/***********************************************************************
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/***********************************************************************
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* brw_eu_util.c:
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*/
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@ -399,7 +399,7 @@ void brw_copy8(struct brw_compile *p,
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struct brw_reg src,
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GLuint count);
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void brw_math_invert( struct brw_compile *p,
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void brw_math_invert( struct brw_compile *p,
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struct brw_reg dst,
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struct brw_reg src);
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|
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@ -2,7 +2,7 @@
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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develop this 3D driver.
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|
||||
|
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Permission is hereby granted, free of charge, to any person obtaining
|
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a copy of this software and associated documentation files (the
|
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"Software"), to deal in the Software without restriction, including
|
||||
|
@ -10,11 +10,11 @@
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distribute, sublicense, and/or sell copies of the Software, and to
|
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permit persons to whom the Software is furnished to do so, subject to
|
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the following conditions:
|
||||
|
||||
|
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The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
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|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
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|
@ -22,13 +22,13 @@
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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*/
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#include "brw_context.h"
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#include "brw_defines.h"
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@ -114,7 +114,7 @@ brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
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insn->bits1.da1.dest_reg_type = dest.type;
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insn->bits1.da1.dest_address_mode = dest.address_mode;
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if (dest.address_mode == BRW_ADDRESS_DIRECT) {
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if (dest.address_mode == BRW_ADDRESS_DIRECT) {
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insn->bits1.da1.dest_reg_nr = dest.nr;
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if (insn->header.access_mode == BRW_ALIGN_1) {
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@ -271,13 +271,13 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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insn->bits3.ud = reg.dw1.ud;
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/* Required to set some fields in src1 as well:
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*/
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insn->bits1.da1.src1_reg_file = 0; /* arf */
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insn->bits1.da1.src1_reg_type = reg.type;
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}
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else
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else
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{
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if (reg.address_mode == BRW_ADDRESS_DIRECT) {
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if (insn->header.access_mode == BRW_ALIGN_1) {
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@ -293,7 +293,7 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
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insn->bits2.ia1.src0_subreg_nr = reg.subnr;
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if (insn->header.access_mode == BRW_ALIGN_1) {
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insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
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insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
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}
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else {
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insn->bits2.ia16.src0_subreg_nr = reg.dw1.bits.indirect_offset;
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@ -301,7 +301,7 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
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}
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if (insn->header.access_mode == BRW_ALIGN_1) {
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if (reg.width == BRW_WIDTH_1 &&
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if (reg.width == BRW_WIDTH_1 &&
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insn->header.execution_size == BRW_EXECUTE_1) {
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insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
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insn->bits2.da1.src0_width = BRW_WIDTH_1;
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@ -373,7 +373,7 @@ void brw_set_src1(struct brw_compile *p,
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}
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if (insn->header.access_mode == BRW_ALIGN_1) {
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if (reg.width == BRW_WIDTH_1 &&
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if (reg.width == BRW_WIDTH_1 &&
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insn->header.execution_size == BRW_EXECUTE_1) {
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insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
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insn->bits3.da1.src1_width = BRW_WIDTH_1;
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@ -735,7 +735,7 @@ brw_next_insn(struct brw_compile *p, GLuint opcode)
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insn = &p->store[p->nr_insn++];
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memcpy(insn, p->current, sizeof(*insn));
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/* Reset this one-shot flag:
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/* Reset this one-shot flag:
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*/
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if (p->current->header.destreg__conditionalmod) {
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@ -764,7 +764,7 @@ static struct brw_instruction *brw_alu2(struct brw_compile *p,
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struct brw_reg src0,
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struct brw_reg src1 )
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{
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struct brw_instruction *insn = next_insn(p, opcode);
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struct brw_instruction *insn = next_insn(p, opcode);
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brw_set_dest(p, insn, dest);
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brw_set_src0(p, insn, src0);
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brw_set_src1(p, insn, src1);
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@ -1058,7 +1058,7 @@ struct brw_instruction *brw_MUL(struct brw_compile *p,
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void brw_NOP(struct brw_compile *p)
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{
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struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
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struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
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brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
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brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
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brw_set_src1(p, insn, brw_imm_ud(0x0));
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@ -1072,7 +1072,7 @@ void brw_NOP(struct brw_compile *p)
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* Comparisons, if/else/endif
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*/
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struct brw_instruction *brw_JMPI(struct brw_compile *p,
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struct brw_instruction *brw_JMPI(struct brw_compile *p,
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struct brw_reg dest,
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struct brw_reg src0,
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struct brw_reg src1)
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@ -1711,7 +1711,7 @@ void brw_CMP(struct brw_compile *p,
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/* Make it so that future instructions will use the computed flag
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* value until brw_set_predicate_control_flag_value() is called
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* again.
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* again.
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*/
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if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
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dest.nr == 0) {
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@ -2318,7 +2318,7 @@ void brw_urb_WRITE(struct brw_compile *p,
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insn,
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flags,
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msg_length,
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response_length,
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response_length,
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offset,
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swizzle);
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}
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|
|
|
@ -2,7 +2,7 @@
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
|
||||
Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
|
||||
develop this 3D driver.
|
||||
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
|
@ -10,11 +10,11 @@
|
|||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
|
@ -22,29 +22,29 @@
|
|||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
**********************************************************************/
|
||||
/*
|
||||
* Authors:
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
*/
|
||||
|
||||
|
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|
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#include "brw_context.h"
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#include "brw_defines.h"
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#include "brw_eu.h"
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|
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|
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void brw_math_invert( struct brw_compile *p,
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void brw_math_invert( struct brw_compile *p,
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struct brw_reg dst,
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struct brw_reg src)
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{
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brw_math( p,
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brw_math( p,
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dst,
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BRW_MATH_FUNCTION_INV,
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BRW_MATH_FUNCTION_INV,
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0,
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src,
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BRW_MATH_PRECISION_FULL,
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BRW_MATH_PRECISION_FULL,
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BRW_MATH_DATA_VECTOR );
|
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}
|
||||
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
Copyright (C) Intel Corp. 2006. All Rights Reserved.
|
||||
Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
|
||||
develop this 3D driver.
|
||||
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
|
@ -10,11 +10,11 @@
|
|||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
|
@ -22,13 +22,13 @@
|
|||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
|
||||
**********************************************************************/
|
||||
/*
|
||||
* Authors:
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
*/
|
||||
|
||||
|
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|
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#ifndef BRW_STRUCTS_H
|
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#define BRW_STRUCTS_H
|
||||
|
@ -37,30 +37,30 @@ struct brw_urb_fence
|
|||
{
|
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struct
|
||||
{
|
||||
GLuint length:8;
|
||||
GLuint vs_realloc:1;
|
||||
GLuint gs_realloc:1;
|
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GLuint clp_realloc:1;
|
||||
GLuint sf_realloc:1;
|
||||
GLuint vfe_realloc:1;
|
||||
GLuint cs_realloc:1;
|
||||
GLuint length:8;
|
||||
GLuint vs_realloc:1;
|
||||
GLuint gs_realloc:1;
|
||||
GLuint clp_realloc:1;
|
||||
GLuint sf_realloc:1;
|
||||
GLuint vfe_realloc:1;
|
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GLuint cs_realloc:1;
|
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GLuint pad:2;
|
||||
GLuint opcode:16;
|
||||
GLuint opcode:16;
|
||||
} header;
|
||||
|
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struct
|
||||
{
|
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GLuint vs_fence:10;
|
||||
GLuint gs_fence:10;
|
||||
GLuint clp_fence:10;
|
||||
GLuint vs_fence:10;
|
||||
GLuint gs_fence:10;
|
||||
GLuint clp_fence:10;
|
||||
GLuint pad:2;
|
||||
} bits0;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint sf_fence:10;
|
||||
GLuint vf_fence:10;
|
||||
GLuint cs_fence:11;
|
||||
GLuint sf_fence:10;
|
||||
GLuint vf_fence:10;
|
||||
GLuint cs_fence:11;
|
||||
GLuint pad:1;
|
||||
} bits1;
|
||||
};
|
||||
|
@ -72,46 +72,46 @@ struct brw_urb_fence
|
|||
struct thread0
|
||||
{
|
||||
GLuint pad0:1;
|
||||
GLuint grf_reg_count:3;
|
||||
GLuint grf_reg_count:3;
|
||||
GLuint pad1:2;
|
||||
GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
|
||||
};
|
||||
|
||||
struct thread1
|
||||
{
|
||||
GLuint ext_halt_exception_enable:1;
|
||||
GLuint sw_exception_enable:1;
|
||||
GLuint mask_stack_exception_enable:1;
|
||||
GLuint timeout_exception_enable:1;
|
||||
GLuint illegal_op_exception_enable:1;
|
||||
GLuint ext_halt_exception_enable:1;
|
||||
GLuint sw_exception_enable:1;
|
||||
GLuint mask_stack_exception_enable:1;
|
||||
GLuint timeout_exception_enable:1;
|
||||
GLuint illegal_op_exception_enable:1;
|
||||
GLuint pad0:3;
|
||||
GLuint depth_coef_urb_read_offset:6; /* WM only */
|
||||
GLuint pad1:2;
|
||||
GLuint floating_point_mode:1;
|
||||
GLuint thread_priority:1;
|
||||
GLuint binding_table_entry_count:8;
|
||||
GLuint floating_point_mode:1;
|
||||
GLuint thread_priority:1;
|
||||
GLuint binding_table_entry_count:8;
|
||||
GLuint pad3:5;
|
||||
GLuint single_program_flow:1;
|
||||
GLuint single_program_flow:1;
|
||||
};
|
||||
|
||||
struct thread2
|
||||
{
|
||||
GLuint per_thread_scratch_space:4;
|
||||
GLuint per_thread_scratch_space:4;
|
||||
GLuint pad0:6;
|
||||
GLuint scratch_space_base_pointer:22;
|
||||
GLuint scratch_space_base_pointer:22;
|
||||
};
|
||||
|
||||
|
||||
|
||||
struct thread3
|
||||
{
|
||||
GLuint dispatch_grf_start_reg:4;
|
||||
GLuint urb_entry_read_offset:6;
|
||||
GLuint dispatch_grf_start_reg:4;
|
||||
GLuint urb_entry_read_offset:6;
|
||||
GLuint pad0:1;
|
||||
GLuint urb_entry_read_length:6;
|
||||
GLuint urb_entry_read_length:6;
|
||||
GLuint pad1:1;
|
||||
GLuint const_urb_entry_read_offset:6;
|
||||
GLuint const_urb_entry_read_offset:6;
|
||||
GLuint pad2:1;
|
||||
GLuint const_urb_entry_read_length:6;
|
||||
GLuint const_urb_entry_read_length:6;
|
||||
GLuint pad3:1;
|
||||
};
|
||||
|
||||
|
@ -143,41 +143,41 @@ struct brw_clip_unit_state
|
|||
{
|
||||
GLuint pad0:9;
|
||||
GLuint gs_output_stats:1; /* not always */
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint pad1:1;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint pad2:1;
|
||||
GLuint max_threads:5; /* may be less */
|
||||
GLuint pad3:2;
|
||||
} thread4;
|
||||
|
||||
} thread4;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad0:13;
|
||||
GLuint clip_mode:3;
|
||||
GLuint userclip_enable_flags:8;
|
||||
GLuint userclip_must_clip:1;
|
||||
GLuint clip_mode:3;
|
||||
GLuint userclip_enable_flags:8;
|
||||
GLuint userclip_must_clip:1;
|
||||
GLuint negative_w_clip_test:1;
|
||||
GLuint guard_band_enable:1;
|
||||
GLuint viewport_z_clip_enable:1;
|
||||
GLuint viewport_xy_clip_enable:1;
|
||||
GLuint vertex_position_space:1;
|
||||
GLuint api_mode:1;
|
||||
GLuint guard_band_enable:1;
|
||||
GLuint viewport_z_clip_enable:1;
|
||||
GLuint viewport_xy_clip_enable:1;
|
||||
GLuint vertex_position_space:1;
|
||||
GLuint api_mode:1;
|
||||
GLuint pad2:1;
|
||||
} clip5;
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad0:5;
|
||||
GLuint clipper_viewport_state_ptr:27;
|
||||
GLuint clipper_viewport_state_ptr:27;
|
||||
} clip6;
|
||||
|
||||
|
||||
GLfloat viewport_xmin;
|
||||
GLfloat viewport_xmax;
|
||||
GLfloat viewport_ymin;
|
||||
GLfloat viewport_ymax;
|
||||
|
||||
GLfloat viewport_xmin;
|
||||
GLfloat viewport_xmax;
|
||||
GLfloat viewport_ymin;
|
||||
GLfloat viewport_ymax;
|
||||
};
|
||||
|
||||
struct gen6_blend_state
|
||||
|
@ -285,88 +285,88 @@ struct brw_cc_unit_state
|
|||
struct
|
||||
{
|
||||
GLuint pad0:3;
|
||||
GLuint bf_stencil_pass_depth_pass_op:3;
|
||||
GLuint bf_stencil_pass_depth_fail_op:3;
|
||||
GLuint bf_stencil_fail_op:3;
|
||||
GLuint bf_stencil_func:3;
|
||||
GLuint bf_stencil_enable:1;
|
||||
GLuint bf_stencil_pass_depth_pass_op:3;
|
||||
GLuint bf_stencil_pass_depth_fail_op:3;
|
||||
GLuint bf_stencil_fail_op:3;
|
||||
GLuint bf_stencil_func:3;
|
||||
GLuint bf_stencil_enable:1;
|
||||
GLuint pad1:2;
|
||||
GLuint stencil_write_enable:1;
|
||||
GLuint stencil_pass_depth_pass_op:3;
|
||||
GLuint stencil_pass_depth_fail_op:3;
|
||||
GLuint stencil_fail_op:3;
|
||||
GLuint stencil_func:3;
|
||||
GLuint stencil_enable:1;
|
||||
GLuint stencil_write_enable:1;
|
||||
GLuint stencil_pass_depth_pass_op:3;
|
||||
GLuint stencil_pass_depth_fail_op:3;
|
||||
GLuint stencil_fail_op:3;
|
||||
GLuint stencil_func:3;
|
||||
GLuint stencil_enable:1;
|
||||
} cc0;
|
||||
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint bf_stencil_ref:8;
|
||||
GLuint stencil_write_mask:8;
|
||||
GLuint stencil_test_mask:8;
|
||||
GLuint stencil_ref:8;
|
||||
GLuint bf_stencil_ref:8;
|
||||
GLuint stencil_write_mask:8;
|
||||
GLuint stencil_test_mask:8;
|
||||
GLuint stencil_ref:8;
|
||||
} cc1;
|
||||
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint logicop_enable:1;
|
||||
GLuint logicop_enable:1;
|
||||
GLuint pad0:10;
|
||||
GLuint depth_write_enable:1;
|
||||
GLuint depth_test_function:3;
|
||||
GLuint depth_test:1;
|
||||
GLuint bf_stencil_write_mask:8;
|
||||
GLuint bf_stencil_test_mask:8;
|
||||
GLuint depth_write_enable:1;
|
||||
GLuint depth_test_function:3;
|
||||
GLuint depth_test:1;
|
||||
GLuint bf_stencil_write_mask:8;
|
||||
GLuint bf_stencil_test_mask:8;
|
||||
} cc2;
|
||||
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad0:8;
|
||||
GLuint alpha_test_func:3;
|
||||
GLuint alpha_test:1;
|
||||
GLuint blend_enable:1;
|
||||
GLuint ia_blend_enable:1;
|
||||
GLuint alpha_test_func:3;
|
||||
GLuint alpha_test:1;
|
||||
GLuint blend_enable:1;
|
||||
GLuint ia_blend_enable:1;
|
||||
GLuint pad1:1;
|
||||
GLuint alpha_test_format:1;
|
||||
GLuint pad2:16;
|
||||
} cc3;
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad0:5;
|
||||
GLuint pad0:5;
|
||||
GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
|
||||
} cc4;
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad0:2;
|
||||
GLuint ia_dest_blend_factor:5;
|
||||
GLuint ia_src_blend_factor:5;
|
||||
GLuint ia_blend_function:3;
|
||||
GLuint statistics_enable:1;
|
||||
GLuint logicop_func:4;
|
||||
GLuint ia_dest_blend_factor:5;
|
||||
GLuint ia_src_blend_factor:5;
|
||||
GLuint ia_blend_function:3;
|
||||
GLuint statistics_enable:1;
|
||||
GLuint logicop_func:4;
|
||||
GLuint pad1:11;
|
||||
GLuint dither_enable:1;
|
||||
GLuint dither_enable:1;
|
||||
} cc5;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint clamp_post_alpha_blend:1;
|
||||
GLuint clamp_pre_alpha_blend:1;
|
||||
GLuint clamp_range:2;
|
||||
GLuint clamp_post_alpha_blend:1;
|
||||
GLuint clamp_pre_alpha_blend:1;
|
||||
GLuint clamp_range:2;
|
||||
GLuint pad0:11;
|
||||
GLuint y_dither_offset:2;
|
||||
GLuint x_dither_offset:2;
|
||||
GLuint dest_blend_factor:5;
|
||||
GLuint src_blend_factor:5;
|
||||
GLuint blend_function:3;
|
||||
GLuint y_dither_offset:2;
|
||||
GLuint x_dither_offset:2;
|
||||
GLuint dest_blend_factor:5;
|
||||
GLuint src_blend_factor:5;
|
||||
GLuint blend_function:3;
|
||||
} cc6;
|
||||
|
||||
struct {
|
||||
union {
|
||||
GLfloat f;
|
||||
GLfloat f;
|
||||
GLubyte ub[4];
|
||||
} alpha_ref;
|
||||
} cc7;
|
||||
|
@ -382,51 +382,51 @@ struct brw_sf_unit_state
|
|||
struct
|
||||
{
|
||||
GLuint pad0:10;
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint pad1:1;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint pad2:1;
|
||||
GLuint max_threads:6;
|
||||
GLuint max_threads:6;
|
||||
GLuint pad3:1;
|
||||
} thread4;
|
||||
} thread4;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint front_winding:1;
|
||||
GLuint viewport_transform:1;
|
||||
GLuint front_winding:1;
|
||||
GLuint viewport_transform:1;
|
||||
GLuint pad0:3;
|
||||
GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
|
||||
} sf5;
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad0:9;
|
||||
GLuint dest_org_vbias:4;
|
||||
GLuint dest_org_hbias:4;
|
||||
GLuint scissor:1;
|
||||
GLuint disable_2x2_trifilter:1;
|
||||
GLuint disable_zero_pix_trifilter:1;
|
||||
GLuint point_rast_rule:2;
|
||||
GLuint line_endcap_aa_region_width:2;
|
||||
GLuint line_width:4;
|
||||
GLuint fast_scissor_disable:1;
|
||||
GLuint cull_mode:2;
|
||||
GLuint aa_enable:1;
|
||||
GLuint dest_org_vbias:4;
|
||||
GLuint dest_org_hbias:4;
|
||||
GLuint scissor:1;
|
||||
GLuint disable_2x2_trifilter:1;
|
||||
GLuint disable_zero_pix_trifilter:1;
|
||||
GLuint point_rast_rule:2;
|
||||
GLuint line_endcap_aa_region_width:2;
|
||||
GLuint line_width:4;
|
||||
GLuint fast_scissor_disable:1;
|
||||
GLuint cull_mode:2;
|
||||
GLuint aa_enable:1;
|
||||
} sf6;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint point_size:11;
|
||||
GLuint use_point_size_state:1;
|
||||
GLuint subpixel_precision:1;
|
||||
GLuint sprite_point:1;
|
||||
GLuint point_size:11;
|
||||
GLuint use_point_size_state:1;
|
||||
GLuint subpixel_precision:1;
|
||||
GLuint sprite_point:1;
|
||||
GLuint pad0:10;
|
||||
GLuint aa_line_distance_mode:1;
|
||||
GLuint trifan_pv:2;
|
||||
GLuint linestrip_pv:2;
|
||||
GLuint tristrip_pv:2;
|
||||
GLuint line_last_pixel_enable:1;
|
||||
GLuint trifan_pv:2;
|
||||
GLuint linestrip_pv:2;
|
||||
GLuint tristrip_pv:2;
|
||||
GLuint line_last_pixel_enable:1;
|
||||
} sf7;
|
||||
|
||||
};
|
||||
|
@ -451,33 +451,33 @@ struct brw_gs_unit_state
|
|||
GLuint pad0:8;
|
||||
GLuint rendering_enable:1; /* for Ironlake */
|
||||
GLuint pad4:1;
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint pad1:1;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint pad2:1;
|
||||
GLuint max_threads:5;
|
||||
GLuint max_threads:5;
|
||||
GLuint pad3:2;
|
||||
} thread4;
|
||||
|
||||
} thread4;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint sampler_count:3;
|
||||
GLuint sampler_count:3;
|
||||
GLuint pad0:2;
|
||||
GLuint sampler_state_pointer:27;
|
||||
GLuint sampler_state_pointer:27;
|
||||
} gs5;
|
||||
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint max_vp_index:4;
|
||||
GLuint max_vp_index:4;
|
||||
GLuint pad0:12;
|
||||
GLuint svbi_post_inc_value:10;
|
||||
GLuint pad1:1;
|
||||
GLuint svbi_post_inc_enable:1;
|
||||
GLuint svbi_payload:1;
|
||||
GLuint discard_adjaceny:1;
|
||||
GLuint reorder_enable:1;
|
||||
GLuint reorder_enable:1;
|
||||
GLuint pad2:1;
|
||||
} gs6;
|
||||
};
|
||||
|
@ -489,30 +489,30 @@ struct brw_vs_unit_state
|
|||
struct thread1 thread1;
|
||||
struct thread2 thread2;
|
||||
struct thread3 thread3;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad0:10;
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint pad1:1;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint pad2:1;
|
||||
GLuint max_threads:6;
|
||||
GLuint pad3:1;
|
||||
} thread4;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint sampler_count:3;
|
||||
GLuint pad0:10;
|
||||
GLuint stats_enable:1;
|
||||
GLuint nr_urb_entries:7;
|
||||
GLuint pad1:1;
|
||||
GLuint urb_entry_allocation_size:5;
|
||||
GLuint pad2:1;
|
||||
GLuint max_threads:6;
|
||||
GLuint pad3:1;
|
||||
} thread4;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint sampler_count:3;
|
||||
GLuint pad0:2;
|
||||
GLuint sampler_state_pointer:27;
|
||||
GLuint sampler_state_pointer:27;
|
||||
} vs5;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint vs_enable:1;
|
||||
GLuint vert_cache_disable:1;
|
||||
GLuint vs_enable:1;
|
||||
GLuint vert_cache_disable:1;
|
||||
GLuint pad0:30;
|
||||
} vs6;
|
||||
};
|
||||
|
@ -524,19 +524,19 @@ struct brw_wm_unit_state
|
|||
struct thread1 thread1;
|
||||
struct thread2 thread2;
|
||||
struct thread3 thread3;
|
||||
|
||||
|
||||
struct {
|
||||
GLuint stats_enable:1;
|
||||
GLuint stats_enable:1;
|
||||
GLuint depth_buffer_clear:1;
|
||||
GLuint sampler_count:3;
|
||||
GLuint sampler_state_pointer:27;
|
||||
GLuint sampler_count:3;
|
||||
GLuint sampler_state_pointer:27;
|
||||
} wm4;
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint enable_8_pix:1;
|
||||
GLuint enable_16_pix:1;
|
||||
GLuint enable_32_pix:1;
|
||||
GLuint enable_8_pix:1;
|
||||
GLuint enable_16_pix:1;
|
||||
GLuint enable_32_pix:1;
|
||||
GLuint enable_con_32_pix:1;
|
||||
GLuint enable_con_64_pix:1;
|
||||
GLuint pad0:1;
|
||||
|
@ -547,46 +547,46 @@ struct brw_wm_unit_state
|
|||
GLuint depth_buffer_resolve_enable:1;
|
||||
GLuint hierarchical_depth_buffer_resolve_enable:1;
|
||||
|
||||
GLuint legacy_global_depth_bias:1;
|
||||
GLuint line_stipple:1;
|
||||
GLuint depth_offset:1;
|
||||
GLuint polygon_stipple:1;
|
||||
GLuint line_aa_region_width:2;
|
||||
GLuint line_endcap_aa_region_width:2;
|
||||
GLuint early_depth_test:1;
|
||||
GLuint thread_dispatch_enable:1;
|
||||
GLuint program_uses_depth:1;
|
||||
GLuint program_computes_depth:1;
|
||||
GLuint program_uses_killpixel:1;
|
||||
GLuint legacy_line_rast: 1;
|
||||
GLuint transposed_urb_read_enable:1;
|
||||
GLuint max_threads:7;
|
||||
GLuint legacy_global_depth_bias:1;
|
||||
GLuint line_stipple:1;
|
||||
GLuint depth_offset:1;
|
||||
GLuint polygon_stipple:1;
|
||||
GLuint line_aa_region_width:2;
|
||||
GLuint line_endcap_aa_region_width:2;
|
||||
GLuint early_depth_test:1;
|
||||
GLuint thread_dispatch_enable:1;
|
||||
GLuint program_uses_depth:1;
|
||||
GLuint program_computes_depth:1;
|
||||
GLuint program_uses_killpixel:1;
|
||||
GLuint legacy_line_rast: 1;
|
||||
GLuint transposed_urb_read_enable:1;
|
||||
GLuint max_threads:7;
|
||||
} wm5;
|
||||
|
||||
GLfloat global_depth_offset_constant;
|
||||
GLfloat global_depth_offset_scale;
|
||||
|
||||
|
||||
GLfloat global_depth_offset_constant;
|
||||
GLfloat global_depth_offset_scale;
|
||||
|
||||
/* for Ironlake only */
|
||||
struct {
|
||||
GLuint pad0:1;
|
||||
GLuint grf_reg_count_1:3;
|
||||
GLuint grf_reg_count_1:3;
|
||||
GLuint pad1:2;
|
||||
GLuint kernel_start_pointer_1:26;
|
||||
} wm8;
|
||||
} wm8;
|
||||
|
||||
struct {
|
||||
GLuint pad0:1;
|
||||
GLuint grf_reg_count_2:3;
|
||||
GLuint grf_reg_count_2:3;
|
||||
GLuint pad1:2;
|
||||
GLuint kernel_start_pointer_2:26;
|
||||
} wm9;
|
||||
} wm9;
|
||||
|
||||
struct {
|
||||
GLuint pad0:1;
|
||||
GLuint grf_reg_count_3:3;
|
||||
GLuint grf_reg_count_3:3;
|
||||
GLuint pad1:2;
|
||||
GLuint kernel_start_pointer_3:26;
|
||||
} wm10;
|
||||
} wm10;
|
||||
};
|
||||
|
||||
struct brw_sampler_default_color {
|
||||
|
@ -604,51 +604,51 @@ struct gen5_sampler_default_color {
|
|||
|
||||
struct brw_sampler_state
|
||||
{
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint shadow_function:3;
|
||||
GLuint lod_bias:11;
|
||||
GLuint min_filter:3;
|
||||
GLuint mag_filter:3;
|
||||
GLuint mip_filter:2;
|
||||
GLuint base_level:5;
|
||||
GLuint shadow_function:3;
|
||||
GLuint lod_bias:11;
|
||||
GLuint min_filter:3;
|
||||
GLuint mag_filter:3;
|
||||
GLuint mip_filter:2;
|
||||
GLuint base_level:5;
|
||||
GLuint min_mag_neq:1;
|
||||
GLuint lod_preclamp:1;
|
||||
GLuint default_color_mode:1;
|
||||
GLuint lod_preclamp:1;
|
||||
GLuint default_color_mode:1;
|
||||
GLuint pad0:1;
|
||||
GLuint disable:1;
|
||||
GLuint disable:1;
|
||||
} ss0;
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint r_wrap_mode:3;
|
||||
GLuint t_wrap_mode:3;
|
||||
GLuint s_wrap_mode:3;
|
||||
GLuint r_wrap_mode:3;
|
||||
GLuint t_wrap_mode:3;
|
||||
GLuint s_wrap_mode:3;
|
||||
GLuint cube_control_mode:1;
|
||||
GLuint pad:2;
|
||||
GLuint max_lod:10;
|
||||
GLuint min_lod:10;
|
||||
GLuint max_lod:10;
|
||||
GLuint min_lod:10;
|
||||
} ss1;
|
||||
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint pad:5;
|
||||
GLuint default_color_pointer:27;
|
||||
GLuint default_color_pointer:27;
|
||||
} ss2;
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
GLuint non_normalized_coord:1;
|
||||
GLuint pad:12;
|
||||
GLuint address_round:6;
|
||||
GLuint max_aniso:3;
|
||||
GLuint chroma_key_mode:1;
|
||||
GLuint chroma_key_index:2;
|
||||
GLuint chroma_key_enable:1;
|
||||
GLuint monochrome_filter_width:3;
|
||||
GLuint monochrome_filter_height:3;
|
||||
GLuint max_aniso:3;
|
||||
GLuint chroma_key_mode:1;
|
||||
GLuint chroma_key_index:2;
|
||||
GLuint chroma_key_enable:1;
|
||||
GLuint monochrome_filter_width:3;
|
||||
GLuint monochrome_filter_height:3;
|
||||
} ss3;
|
||||
};
|
||||
|
||||
|
@ -703,27 +703,27 @@ struct gen7_sampler_state
|
|||
|
||||
struct brw_clipper_viewport
|
||||
{
|
||||
GLfloat xmin;
|
||||
GLfloat xmax;
|
||||
GLfloat ymin;
|
||||
GLfloat ymax;
|
||||
GLfloat xmin;
|
||||
GLfloat xmax;
|
||||
GLfloat ymin;
|
||||
GLfloat ymax;
|
||||
};
|
||||
|
||||
struct brw_cc_viewport
|
||||
{
|
||||
GLfloat min_depth;
|
||||
GLfloat max_depth;
|
||||
GLfloat min_depth;
|
||||
GLfloat max_depth;
|
||||
};
|
||||
|
||||
struct brw_sf_viewport
|
||||
{
|
||||
struct {
|
||||
GLfloat m00;
|
||||
GLfloat m11;
|
||||
GLfloat m22;
|
||||
GLfloat m30;
|
||||
GLfloat m31;
|
||||
GLfloat m32;
|
||||
GLfloat m00;
|
||||
GLfloat m11;
|
||||
GLfloat m22;
|
||||
GLfloat m30;
|
||||
GLfloat m31;
|
||||
GLfloat m32;
|
||||
} viewport;
|
||||
|
||||
/* scissor coordinates are inclusive */
|
||||
|
@ -769,7 +769,7 @@ struct gen7_sf_clip_viewport {
|
|||
struct brw_urb_immediate {
|
||||
GLuint opcode:4;
|
||||
GLuint offset:6;
|
||||
GLuint swizzle_control:2;
|
||||
GLuint swizzle_control:2;
|
||||
GLuint pad:1;
|
||||
GLuint allocate:1;
|
||||
GLuint used:1;
|
||||
|
@ -783,10 +783,10 @@ struct brw_urb_immediate {
|
|||
|
||||
/* Instruction format for the execution units:
|
||||
*/
|
||||
|
||||
|
||||
struct brw_instruction
|
||||
{
|
||||
struct
|
||||
struct
|
||||
{
|
||||
GLuint opcode:7;
|
||||
GLuint pad:1;
|
||||
|
@ -981,7 +981,7 @@ struct brw_instruction
|
|||
* Does not apply to Gen6+. The SFID/message target moved to bits
|
||||
* 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
|
||||
*/
|
||||
struct
|
||||
struct
|
||||
{
|
||||
GLuint pad:26;
|
||||
GLuint end_of_thread:1;
|
||||
|
@ -1165,8 +1165,8 @@ struct brw_instruction
|
|||
struct {
|
||||
GLuint binding_table_index:8;
|
||||
GLuint sampler:4;
|
||||
GLuint return_format:2;
|
||||
GLuint msg_type:2;
|
||||
GLuint return_format:2;
|
||||
GLuint msg_type:2;
|
||||
GLuint response_length:4;
|
||||
GLuint msg_length:4;
|
||||
GLuint msg_target:4;
|
||||
|
@ -1217,7 +1217,7 @@ struct brw_instruction
|
|||
struct {
|
||||
GLuint opcode:4;
|
||||
GLuint offset:6;
|
||||
GLuint swizzle_control:2;
|
||||
GLuint swizzle_control:2;
|
||||
GLuint pad:1;
|
||||
GLuint allocate:1;
|
||||
GLuint used:1;
|
||||
|
@ -1247,9 +1247,9 @@ struct brw_instruction
|
|||
/** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
|
||||
struct {
|
||||
GLuint binding_table_index:8;
|
||||
GLuint msg_control:4;
|
||||
GLuint msg_type:2;
|
||||
GLuint target_cache:2;
|
||||
GLuint msg_control:4;
|
||||
GLuint msg_type:2;
|
||||
GLuint target_cache:2;
|
||||
GLuint response_length:4;
|
||||
GLuint msg_length:4;
|
||||
GLuint msg_target:4;
|
||||
|
@ -1273,9 +1273,9 @@ struct brw_instruction
|
|||
/** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
|
||||
struct {
|
||||
GLuint binding_table_index:8;
|
||||
GLuint msg_control:3;
|
||||
GLuint msg_type:3;
|
||||
GLuint target_cache:2;
|
||||
GLuint msg_control:3;
|
||||
GLuint msg_type:3;
|
||||
GLuint target_cache:2;
|
||||
GLuint pad0:3;
|
||||
GLuint header_present:1;
|
||||
GLuint response_length:5;
|
||||
|
@ -1289,7 +1289,7 @@ struct brw_instruction
|
|||
GLuint binding_table_index:8;
|
||||
GLuint msg_control:3;
|
||||
GLuint last_render_target:1;
|
||||
GLuint msg_type:3;
|
||||
GLuint msg_type:3;
|
||||
GLuint send_commit_msg:1;
|
||||
GLuint response_length:4;
|
||||
GLuint msg_length:4;
|
||||
|
@ -1303,7 +1303,7 @@ struct brw_instruction
|
|||
GLuint binding_table_index:8;
|
||||
GLuint msg_control:3;
|
||||
GLuint last_render_target:1;
|
||||
GLuint msg_type:3;
|
||||
GLuint msg_type:3;
|
||||
GLuint send_commit_msg:1;
|
||||
GLuint pad0:3;
|
||||
GLuint header_present:1;
|
||||
|
|
Loading…
Reference in New Issue