freedreno/fdl6: rework layout code a bit (reduce linear align to 64 bytes)
Reduce linear alignment, and rework the layout code a bit. This rework has a side effect of also increasing the alignment on linear levels of tiled (non-ubwc) cpp=1 and cpp=2 layouts. Since we should be UBWC for those cases anyway, its not a big loss. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5013>
This commit is contained in:
Jonathan Marek
Marge Bot
parent
3a9ab3b6e9
commit
d53dc6c376
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@ -29,62 +29,70 @@
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#include "freedreno_layout.h"
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/* indexed by cpp, including msaa 2x and 4x:
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* TODO:
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* cpp=1 UBWC needs testing at larger texture sizes
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* missing UBWC blockwidth/blockheight for npot+64 cpp
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* missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
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*/
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static const struct tile_alignment {
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unsigned basealign;
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unsigned pitchalign;
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unsigned heightalign;
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/* UBWC block width/height. Used in size alignment, and calculating a
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* descriptor's FLAG_BUFFER_LOG2W/H for mipmapping.
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*/
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uint8_t ubwc_blockwidth;
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uint8_t ubwc_blockheight;
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} tile_alignment[] = {
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[1] = { 64, 128, 32, 16, 4 },
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[2] = { 128, 128, 16, 16, 4 },
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[3] = { 256, 64, 32 },
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[4] = { 256, 64, 16, 16, 4 },
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[6] = { 256, 64, 16 },
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[8] = { 256, 64, 16, 8, 4, },
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[12] = { 256, 64, 16 },
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[16] = { 256, 64, 16, 4, 4, },
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[24] = { 256, 64, 16 },
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[32] = { 256, 64, 16, 4, 2 },
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[48] = { 256, 64, 16 },
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[64] = { 256, 64, 16 },
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/* special cases for r8g8: */
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[0] = { 256, 64, 32, 16, 8 },
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};
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#define RGB_TILE_WIDTH_ALIGNMENT 64
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#define RGB_TILE_HEIGHT_ALIGNMENT 16
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#define UBWC_PLANE_SIZE_ALIGNMENT 4096
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static const struct tile_alignment *
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fdl6_tile_alignment(struct fdl_layout *layout)
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static bool
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is_r8g8(struct fdl_layout *layout)
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{
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debug_assert(layout->cpp < ARRAY_SIZE(tile_alignment));
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if ((layout->cpp == 2) && (util_format_get_nr_components(layout->format) == 2))
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return &tile_alignment[0];
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else
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return &tile_alignment[layout->cpp];
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return layout->cpp == 2 &&
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util_format_get_nr_components(layout->format) == 2;
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}
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static int
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fdl6_pitchalign(struct fdl_layout *layout, int level)
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void
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fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
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uint32_t *blockwidth, uint32_t *blockheight)
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{
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uint32_t pitchalign = 64;
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if (fdl_tile_mode(layout, level))
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pitchalign = fdl6_tile_alignment(layout)->pitchalign;
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static const struct {
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uint8_t width;
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uint8_t height;
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} blocksize[] = {
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{ 16, 4 }, /* cpp = 1 */
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{ 16, 4 }, /* cpp = 2 */
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{ 16, 4 }, /* cpp = 4 */
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{ 8, 4, }, /* cpp = 8 */
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{ 4, 4, }, /* cpp = 16 */
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{ 4, 2 }, /* cpp = 32 */
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{ 0, 0 }, /* cpp = 64 (TODO) */
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};
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return pitchalign;
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/* special case for r8g8: */
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if (is_r8g8(layout)) {
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*blockwidth = 16;
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*blockheight = 8;
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return;
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}
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uint32_t cpp = fdl_cpp_shift(layout);
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assert(cpp < ARRAY_SIZE(blocksize));
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*blockwidth = blocksize[cpp].width;
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*blockheight = blocksize[cpp].height;
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}
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static void
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fdl6_tile_alignment(struct fdl_layout *layout, uint32_t *heightalign)
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{
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layout->pitchalign = fdl_cpp_shift(layout);
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*heightalign = 16;
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if (is_r8g8(layout) || layout->cpp == 1) {
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layout->pitchalign = 1;
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*heightalign = 32;
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} else if (layout->cpp == 2) {
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layout->pitchalign = 2;
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}
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/* note: this base_align is *probably* not always right,
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* it doesn't really get tested. for example with UBWC we might
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* want 4k alignment, since we align UBWC levels to 4k
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*/
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if (layout->cpp == 1)
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layout->base_align = 64;
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else if (layout->cpp == 2)
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layout->base_align = 128;
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else
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layout->base_align = 256;
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}
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/* NOTE: good way to test this is: (for example)
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@ -97,8 +105,9 @@ fdl6_layout(struct fdl_layout *layout,
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uint32_t mip_levels, uint32_t array_size, bool is_3d,
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struct fdl_slice *plane_layout)
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{
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uint32_t offset;
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uint32_t pitch0;
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uint32_t offset, pitch0;
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uint32_t pitchalign, heightalign;
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uint32_t ubwc_blockwidth, ubwc_blockheight;
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assert(nr_samples > 0);
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layout->width0 = width0;
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@ -113,37 +122,54 @@ fdl6_layout(struct fdl_layout *layout,
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layout->nr_samples = nr_samples;
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layout->layer_first = !is_3d;
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if (depth0 > 1)
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layout->ubwc = false;
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if (tile_alignment[layout->cpp].ubwc_blockwidth == 0)
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layout->ubwc = false;
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fdl6_get_ubwc_blockwidth(layout, &ubwc_blockwidth, &ubwc_blockheight);
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const struct tile_alignment *ta = fdl6_tile_alignment(layout);
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if (depth0 > 1 || ubwc_blockwidth == 0)
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layout->ubwc = false;
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/* in layer_first layout, the level (slice) contains just one
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* layer (since in fact the layer contains the slices)
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*/
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uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
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debug_assert(ta->pitchalign);
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/* note: for tiled+noubwc layouts, we can use a lower pitchalign
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* which will affect the linear levels only, (the hardware will still
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* expect the tiled alignment on the tiled levels)
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*/
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if (layout->tile_mode) {
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layout->base_align = ta->basealign;
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fdl6_tile_alignment(layout, &heightalign);
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} else {
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layout->base_align = 64;
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layout->pitchalign = 0;
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/* align pitch to at least 16 pixels:
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* both turnip and galium assume there is enough alignment for 16x4
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* aligned gmem store. turnip can use CP_BLIT to work without this
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* extra alignment, but gallium driver doesn't implement it yet
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*/
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if (layout->cpp > 4)
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layout->pitchalign = fdl_cpp_shift(layout) - 2;
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/* when possible, use a bit more alignment than necessary
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* presumably this is better for performance?
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*/
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if (!plane_layout)
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layout->pitchalign = fdl_cpp_shift(layout);
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/* not used, avoid "may be used uninitialized" warning */
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heightalign = 1;
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}
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pitchalign = 64 << layout->pitchalign;
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if (plane_layout) {
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offset = plane_layout->offset;
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pitch0 = plane_layout->pitch;
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if (align(pitch0, fdl6_pitchalign(layout, 0) * layout->cpp) != pitch0)
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return false;
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pitch0 /= layout->cpp; /* explicit pitch is in bytes */
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if (pitch0 < width0 && height0 > 1)
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if (align(pitch0, pitchalign) != pitch0)
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return false;
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} else {
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uint32_t nblocksx = util_format_get_nblocksx(format, width0);
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offset = 0;
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pitch0 = util_align_npot(width0, fdl6_pitchalign(layout, 0));
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pitch0 = util_align_npot(nblocksx * layout->cpp, pitchalign);
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}
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uint32_t ubwc_width0 = width0;
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@ -159,15 +185,11 @@ fdl6_layout(struct fdl_layout *layout,
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ubwc_height0 = util_next_power_of_two(height0);
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ubwc_tile_height_alignment = 64;
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}
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ubwc_width0 = align(DIV_ROUND_UP(ubwc_width0, ta->ubwc_blockwidth),
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ubwc_width0 = align(DIV_ROUND_UP(ubwc_width0, ubwc_blockwidth),
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RGB_TILE_WIDTH_ALIGNMENT);
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ubwc_height0 = align(DIV_ROUND_UP(ubwc_height0,
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ta->ubwc_blockheight),
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ubwc_height0 = align(DIV_ROUND_UP(ubwc_height0, ubwc_blockheight),
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ubwc_tile_height_alignment);
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layout->pitchalign =
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util_logbase2_ceil(fdl6_pitchalign(layout, mip_levels - 1) * layout->cpp >> 6);
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for (uint32_t level = 0; level < mip_levels; level++) {
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uint32_t depth = u_minify(depth0, level);
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struct fdl_slice *slice = &layout->slices[level];
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@ -184,7 +206,7 @@ fdl6_layout(struct fdl_layout *layout,
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uint32_t nblocksy = util_format_get_nblocksy(format, height);
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if (tile_mode)
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nblocksy = align(nblocksy, ta->heightalign);
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nblocksy = align(nblocksy, heightalign);
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/* The blits used for mem<->gmem work at a granularity of
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* 16x4, which can cause faults due to over-fetch on the
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@ -196,14 +218,8 @@ fdl6_layout(struct fdl_layout *layout,
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if (level == mip_levels - 1)
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height = align(nblocksy, 4);
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uint32_t nblocksx =
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util_align_npot(util_format_get_nblocksx(format, u_minify(pitch0, level)),
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fdl6_pitchalign(layout, level));
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slice->offset = offset + layout->size;
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uint32_t blocks = nblocksx * nblocksy;
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slice->pitch = nblocksx * layout->cpp;
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slice->offset = layout->size;
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slice->pitch = align(u_minify(pitch0, level), pitchalign);
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/* 1d array and 2d array textures must all have the same layer size
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* for each miplevel on a6xx. 3d textures can have different layer
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@ -213,12 +229,12 @@ fdl6_layout(struct fdl_layout *layout,
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*/
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if (is_3d) {
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if (level < 1 || layout->slices[level - 1].size0 > 0xf000) {
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slice->size0 = align(blocks * layout->cpp, 4096);
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slice->size0 = align(nblocksy * slice->pitch, 4096);
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} else {
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slice->size0 = layout->slices[level - 1].size0;
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}
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} else {
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slice->size0 = blocks * layout->cpp;
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slice->size0 = nblocksy * slice->pitch;
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}
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layout->size += slice->size0 * depth * layers_in_level;
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@ -260,12 +276,3 @@ fdl6_layout(struct fdl_layout *layout,
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return true;
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}
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void
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fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
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uint32_t *blockwidth, uint32_t *blockheight)
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{
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const struct tile_alignment *ta = fdl6_tile_alignment(layout);
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*blockwidth = ta->ubwc_blockwidth;
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*blockheight = ta->ubwc_blockheight;
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}
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@ -356,10 +356,10 @@ static const struct testcase testcases[] = {
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{ .offset = 8192, .pitch = 128 },
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{ .offset = 12288, .pitch = 128 },
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{ .offset = 16384, .pitch = 128 },
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{ .offset = 20480, .pitch = 64 },
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{ .offset = 20544, .pitch = 64 },
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{ .offset = 20608, .pitch = 64 },
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{ .offset = 20672, .pitch = 64 },
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{ .offset = 20480, .pitch = 128 },
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{ .offset = 20608, .pitch = 128 },
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{ .offset = 20736, .pitch = 128 },
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{ .offset = 20864, .pitch = 128 },
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},
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},
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},
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@ -1129,10 +1129,6 @@ tu_copy_buffer_to_image(struct tu_cmd_buffer *cmd,
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uint32_t pitch = src_width * vk_format_get_blocksize(src_format);
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uint32_t layer_size = src_height * pitch;
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/* note: the src_va/pitch alignment of 64 is for 2D engine,
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* it is also valid for 1cpp format with shader path (stencil aspect path)
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*/
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ops->setup(cmd, cs, dst_format, ROTATE_0, false, mask);
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struct tu_image_view dst;
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@ -1212,10 +1208,6 @@ tu_copy_image_to_buffer(struct tu_cmd_buffer *cmd,
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uint32_t pitch = dst_width * vk_format_get_blocksize(dst_format);
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uint32_t layer_size = pitch * dst_height;
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/* note: the dst_va/pitch alignment of 64 is for 2D engine,
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* it is also valid for 1cpp format with shader path (stencil aspect)
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*/
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ops->setup(cmd, cs, dst_format, ROTATE_0, false, 0xf);
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struct tu_image_view src;
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@ -1032,9 +1032,11 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
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uint32_t pitchalign = fd_screen(pscreen)->gmem_alignw * rsc->layout.cpp;
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/* use 64 pitchalign on a6xx where gmem_alignw is not right */
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/* pitchalign is 64-bytes for linear formats on a6xx
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* layout_resource_for_modifier will validate tiled pitch
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*/
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if (is_a6xx(screen))
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pitchalign = 64 * rsc->layout.cpp;
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pitchalign = 64;
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if ((slice->pitch < align(prsc->width0 * rsc->layout.cpp, pitchalign)) ||
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(slice->pitch & (pitchalign - 1)))
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