ilo: simplify emit_3DSTATE_DEPTH_BUFFER()
Remove hiz and dsa from the parameters. We would know whether HiZ buffer exists from ilo_texture once it is supported. DSA state should not affect 3DSTATE_DEPTH_BUFFER.
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@ -722,8 +722,7 @@ gen6_pipeline_wm_depth(struct ilo_3d_pipeline *p,
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gen6_wa_pipe_control_wm_depth_flush(p);
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}
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p->gen6_3DSTATE_DEPTH_BUFFER(p->dev,
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ilo->fb.state.zsbuf, false, p->cp);
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p->gen6_3DSTATE_DEPTH_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
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/* TODO */
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p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
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@ -539,16 +539,9 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p,
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*/
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/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
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if (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) ||
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session->state_bo_changed) {
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const bool hiz = false;
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p->gen7_3DSTATE_DEPTH_BUFFER(p->dev,
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ilo->fb.state.zsbuf, &ilo->dsa->state, hiz, p->cp);
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p->gen6_3DSTATE_HIER_DEPTH_BUFFER(p->dev,
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(hiz) ? ilo->fb.state.zsbuf : NULL, p->cp);
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if (DIRTY(FRAMEBUFFER) || session->state_bo_changed) {
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p->gen7_3DSTATE_DEPTH_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
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p->gen6_3DSTATE_HIER_DEPTH_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
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p->gen6_3DSTATE_STENCIL_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
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/* TODO */
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@ -2272,18 +2272,17 @@ gen6_get_depth_buffer_format(const struct ilo_dev_info *dev,
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return depth_format;
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}
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void
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ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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const struct pipe_surface *surface,
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const struct pipe_depth_stencil_alpha_state *dsa,
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bool hiz,
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struct ilo_cp *cp)
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static void
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gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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const struct pipe_surface *surface,
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struct ilo_cp *cp)
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{
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const uint32_t cmd = (dev->gen >= ILO_GEN(7)) ?
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ILO_GPE_CMD(0x3, 0x0, 0x05) : ILO_GPE_CMD(0x3, 0x1, 0x05);
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const uint8_t cmd_len = 7;
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const int max_2d_size = (dev->gen >= ILO_GEN(7)) ? 16384 : 8192;
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const int max_array_size = (dev->gen >= ILO_GEN(7)) ? 2048 : 512;
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const bool hiz = false;
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struct ilo_texture *tex;
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uint32_t dw1, dw3, dw4, dw6;
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uint32_t slice_offset, x_offset, y_offset;
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@ -2465,17 +2464,15 @@ ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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(tex->bo_stride - 1);
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if (dev->gen >= ILO_GEN(7)) {
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if (has_depth) {
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if (dsa->depth.writemask)
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dw1 |= 1 << 28;
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if (hiz)
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dw1 |= 1 << 22;
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}
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if (has_depth)
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dw1 |= 1 << 28;
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if (has_stencil &&
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(dsa->stencil[0].writemask || dsa->stencil[1].writemask))
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if (has_stencil)
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dw1 |= 1 << 27;
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if (hiz)
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dw1 |= 1 << 22;
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dw3 = (height - 1) << 18 |
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(width - 1) << 4 |
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lod;
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@ -2525,15 +2522,6 @@ ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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ilo_cp_end(cp);
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}
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static void
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gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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const struct pipe_surface *surface,
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bool hiz,
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struct ilo_cp *cp)
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{
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ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(dev, surface, NULL, hiz, cp);
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}
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static void
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gen6_emit_3DSTATE_POLY_STIPPLE_OFFSET(const struct ilo_dev_info *dev,
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int x_offset, int y_offset,
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@ -2765,12 +2753,13 @@ gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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ILO_GPE_CMD(0x3, 0x0, 0x07) :
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ILO_GPE_CMD(0x3, 0x1, 0x0f);
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const uint8_t cmd_len = 3;
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const bool hiz = false;
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struct ilo_texture *tex;
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uint32_t slice_offset;
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ILO_GPE_VALID_GEN(dev, 6, 7);
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if (!surface) {
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if (!surface || !hiz) {
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, cmd | (cmd_len - 2));
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ilo_cp_write(cp, 0);
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@ -301,7 +301,6 @@ typedef void
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typedef void
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(*ilo_gpe_gen6_3DSTATE_DEPTH_BUFFER)(const struct ilo_dev_info *dev,
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const struct pipe_surface *surface,
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bool hiz,
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struct ilo_cp *cp);
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typedef void
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@ -569,11 +568,4 @@ ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev,
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const struct ilo_shader *last_sh,
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uint32_t *dw, int num_dwords);
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void
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ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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const struct pipe_surface *surface,
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const struct pipe_depth_stencil_alpha_state *dsa,
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bool hiz,
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struct ilo_cp *cp);
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#endif /* ILO_GPE_GEN6_H */
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@ -58,16 +58,6 @@ gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
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ilo_cp_end(cp);
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}
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static void
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gen7_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
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const struct pipe_surface *surface,
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const struct pipe_depth_stencil_alpha_state *dsa,
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bool hiz,
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struct ilo_cp *cp)
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{
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ilo_gpe_gen6_emit_3DSTATE_DEPTH_BUFFER(dev, surface, dsa, hiz, cp);
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}
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static void
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gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
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int subop, uint32_t pointer,
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@ -1926,7 +1916,7 @@ gen7_init(struct ilo_gpe_gen7 *gen7)
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GEN7_USE(gen7, MEDIA_STATE_FLUSH, gen6);
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GEN7_SET(gen7, GPGPU_WALKER);
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GEN7_SET(gen7, 3DSTATE_CLEAR_PARAMS);
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GEN7_SET(gen7, 3DSTATE_DEPTH_BUFFER);
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GEN7_USE(gen7, 3DSTATE_DEPTH_BUFFER, gen6);
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GEN7_USE(gen7, 3DSTATE_STENCIL_BUFFER, gen6);
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GEN7_USE(gen7, 3DSTATE_HIER_DEPTH_BUFFER, gen6);
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GEN7_USE(gen7, 3DSTATE_VERTEX_BUFFERS, gen6);
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@ -141,14 +141,7 @@ typedef void
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struct ilo_cp *cp);
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typedef ilo_gpe_gen6_3DSTATE_CLEAR_PARAMS ilo_gpe_gen7_3DSTATE_CLEAR_PARAMS;
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typedef void
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(*ilo_gpe_gen7_3DSTATE_DEPTH_BUFFER)(const struct ilo_dev_info *dev,
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const struct pipe_surface *surface,
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const struct pipe_depth_stencil_alpha_state *dsa,
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bool hiz,
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struct ilo_cp *cp);
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typedef ilo_gpe_gen6_3DSTATE_DEPTH_BUFFER ilo_gpe_gen7_3DSTATE_DEPTH_BUFFER;
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typedef ilo_gpe_gen6_3DSTATE_STENCIL_BUFFER ilo_gpe_gen7_3DSTATE_STENCIL_BUFFER;
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typedef ilo_gpe_gen6_3DSTATE_HIER_DEPTH_BUFFER ilo_gpe_gen7_3DSTATE_HIER_DEPTH_BUFFER;
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typedef ilo_gpe_gen6_3DSTATE_VERTEX_BUFFERS ilo_gpe_gen7_3DSTATE_VERTEX_BUFFERS;
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