gallium/radeon: don't allocate DCC for non-renderable texture formats
R9G9B9E5 is the only uncompressed one hopefully. This fixes incorrect rendering not discovered (due to a lack of tests) until DCC mipmapping was enabled. Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -281,6 +281,11 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
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if (rscreen->chip_class >= SI) {
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surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
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}
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if (rscreen->chip_class >= VI &&
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ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
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surface->flags |= RADEON_SURF_DISABLE_DCC;
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return 0;
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}
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@ -342,6 +342,7 @@ enum radeon_feature_id {
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#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
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#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
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#define RADEON_SURF_FMASK (1 << 21)
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#define RADEON_SURF_DISABLE_DCC (1 << 22)
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#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
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#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
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@ -343,6 +343,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
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AddrSurfInfoIn.flags.degrade4Space = 1;
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AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
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!(surf->flags & RADEON_SURF_SCANOUT) &&
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!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
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!compressed && AddrDccIn.numSamples <= 1;
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AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
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