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gallium/radeon: don't allocate DCC for non-renderable texture formats 

R9G9B9E5 is the only uncompressed one hopefully.

This fixes incorrect rendering not discovered (due to a lack of tests)
until DCC mipmapping was enabled.

Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2016-06-06 01:29:14 +02:00
parent b42bc90b6a
commit d4d733e39d
3 changed files with 7 additions and 0 deletions
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5
src/gallium/drivers/radeon/r600_texture.c
View File

@ -281,6 +281,11 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
if (rscreen->chip_class >= SI) {
surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
}
if (rscreen->chip_class >= VI &&
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
surface->flags |= RADEON_SURF_DISABLE_DCC;
return 0;
}

1
src/gallium/drivers/radeon/radeon_winsys.h
View File

@ -342,6 +342,7 @@ enum radeon_feature_id {
#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)

1
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View File

@ -343,6 +343,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.flags.degrade4Space = 1;
AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_SCANOUT) &&
!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
!compressed && AddrDccIn.numSamples <= 1;
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;