vk/cmd_buffer: Move the re-emission of STATE_BASE_ADDRESS to the flushing code
This used to happen magically in cmd_buffer_new_surface_state_bo. However, according to Ken, STATE_BASE_ADDRESS is very gen-specific so we really shouldn't have it in the generic data-structure code.
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@ -345,51 +345,6 @@ anv_cmd_buffer_new_surface_state_bo(struct anv_cmd_buffer *cmd_buffer)
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new_bbo->prev_batch_bo = old_bbo;
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new_bbo->prev_batch_bo = old_bbo;
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cmd_buffer->surface_batch_bo = new_bbo;
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cmd_buffer->surface_batch_bo = new_bbo;
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/* Re-emit state base addresses so we get the new surface state base
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* address before we start emitting binding tables etc.
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*/
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anv_cmd_buffer_emit_state_base_address(cmd_buffer);
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/* After re-setting the surface state base address, we have to do some
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* cache flusing so that the sampler engine will pick up the new
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* SURFACE_STATE objects and binding tables. From the Broadwell PRM,
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* Shared Function > 3D Sampler > State > State Caching (page 96):
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*
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* Coherency with system memory in the state cache, like the texture
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* cache is handled partially by software. It is expected that the
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* command stream or shader will issue Cache Flush operation or
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* Cache_Flush sampler message to ensure that the L1 cache remains
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* coherent with system memory.
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*
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* [...]
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*
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* Whenever the value of the Dynamic_State_Base_Addr,
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* Surface_State_Base_Addr are altered, the L1 state cache must be
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* invalidated to ensure the new surface or sampler state is fetched
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* from system memory.
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*
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* The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
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* which, according the PIPE_CONTROL instruction documentation in the
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* Broadwell PRM:
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*
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* Setting this bit is independent of any other bit in this packet.
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* This bit controls the invalidation of the L1 and L2 state caches
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* at the top of the pipe i.e. at the parsing time.
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*
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* Unfortunately, experimentation seems to indicate that state cache
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* invalidation through a PIPE_CONTROL does nothing whatsoever in
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* regards to surface state and binding tables. In stead, it seems that
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* invalidating the texture cache is what is actually needed.
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*
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* XXX: As far as we have been able to determine through
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* experimentation, shows that flush the texture cache appears to be
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* sufficient. The theory here is that all of the sampling/rendering
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* units cache the binding table in the texture cache. However, we have
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* yet to be able to actually confirm this.
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*/
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anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
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.TextureCacheInvalidationEnable = true);
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return VK_SUCCESS;
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return VK_SUCCESS;
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}
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}
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@ -504,6 +504,51 @@ flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
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result = anv_cmd_buffer_new_surface_state_bo(cmd_buffer);
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result = anv_cmd_buffer_new_surface_state_bo(cmd_buffer);
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assert(result == VK_SUCCESS);
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assert(result == VK_SUCCESS);
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/* Re-emit state base addresses so we get the new surface state base
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* address before we start emitting binding tables etc.
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*/
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anv_cmd_buffer_emit_state_base_address(cmd_buffer);
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/* After re-setting the surface state base address, we have to do
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* some cache flusing so that the sampler engine will pick up the new
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* SURFACE_STATE objects and binding tables. From the Broadwell PRM,
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* Shared Function > 3D Sampler > State > State Caching (page 96):
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*
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* Coherency with system memory in the state cache, like the
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* texture cache is handled partially by software. It is expected
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* that the command stream or shader will issue Cache Flush
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* operation or Cache_Flush sampler message to ensure that the L1
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* cache remains coherent with system memory.
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*
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* [...]
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*
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* Whenever the value of the Dynamic_State_Base_Addr,
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* Surface_State_Base_Addr are altered, the L1 state cache must be
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* invalidated to ensure the new surface or sampler state is
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* fetched from system memory.
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*
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* The PIPE_CONTROL command has a "State Cache Invalidation Enable"
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* bit which, according the PIPE_CONTROL instruction documentation in
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* the Broadwell PRM:
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*
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* Setting this bit is independent of any other bit in this
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* packet. This bit controls the invalidation of the L1 and L2
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* state caches at the top of the pipe i.e. at the parsing time.
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*
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* Unfortunately, experimentation seems to indicate that state cache
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* invalidation through a PIPE_CONTROL does nothing whatsoever in
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* regards to surface state and binding tables. In stead, it seems
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* that invalidating the texture cache is what is actually needed.
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*
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* XXX: As far as we have been able to determine through
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* experimentation, shows that flush the texture cache appears to be
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* sufficient. The theory here is that all of the sampling/rendering
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* units cache the binding table in the texture cache. However, we
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* have yet to be able to actually confirm this.
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*/
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anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
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.TextureCacheInvalidationEnable = true);
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/* Re-emit all active binding tables */
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/* Re-emit all active binding tables */
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for_each_bit(s, cmd_buffer->state.pipeline->active_stages) {
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for_each_bit(s, cmd_buffer->state.pipeline->active_stages) {
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result = flush_descriptor_set(cmd_buffer, s);
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result = flush_descriptor_set(cmd_buffer, s);
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