From d3acc240d0ced4efefd18e8c26510bd6a638c9df Mon Sep 17 00:00:00 2001
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Tue, 3 Oct 2017 16:05:07 +0100
Subject: [PATCH] intel: compiler: vec4: add missing default 0 lod

We set a similar default value for LOD in the fs backend for TXS/TXL.
Without this we end up generating invalid MOV with a null src.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
---
 src/intel/compiler/brw_vec4_nir.cpp | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 0a1caa9fad8..9200ffa0ed7 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -2228,6 +2228,15 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
       }
    }
 
+   /* TXS and TXL require a LOD but not everything we implement using those
+    * two opcodes provides one.  Provide a default LOD of 0.
+    */
+   if ((instr->op == nir_texop_txs ||
+        instr->op == nir_texop_txl) &&
+       lod.file == BAD_FILE) {
+      lod = brw_imm_ud(0u);
+   }
+
    if (instr->op == nir_texop_txf_ms ||
        instr->op == nir_texop_samples_identical) {
       assert(coord_type != NULL);