freedreno/afuc: Split out instruction decode helper
Split the giant switch/decode out into a helper function so that we can re-use it for emulator mode. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10944>
This commit is contained in:
Rob Clark
Marge Bot
parent
33b9445a68
commit
d367d84d87
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@ -300,6 +300,412 @@ print_control_reg(uint32_t id)
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}
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}
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static void
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disasm_instr(uint32_t *instrs, unsigned pc)
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{
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int jump_label_idx;
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afuc_instr *instr = (void *)&instrs[pc];
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const char *fname, *lname;
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afuc_opc opc;
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bool rep;
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afuc_get_opc(instr, &opc, &rep);
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lname = label_name(pc, false);
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fname = fxn_name(pc);
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jump_label_idx = get_jump_table_entry(pc);
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if (jump_label_idx >= 0) {
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int j;
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printf("\n");
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for (j = 0; j < jump_labels[jump_label_idx].num_jump_labels; j++) {
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uint32_t jump_label = jump_labels[jump_label_idx].jump_labels[j];
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const char *name = getpm4(jump_label);
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if (name) {
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printlbl("%s", name);
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} else {
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printlbl("UNKN%d", jump_label);
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}
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printf(":\n");
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}
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}
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if (fname) {
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printlbl("%s", fname);
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printf(":\n");
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}
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if (lname) {
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printlbl(" %s", lname);
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printf(":");
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} else {
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printf(" ");
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}
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if (verbose) {
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printf("\t%04x: %08x ", pc, instrs[pc]);
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} else {
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printf(" ");
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}
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switch (opc) {
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case OPC_NOP: {
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/* a6xx changed the default immediate, and apparently 0
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* is illegal now.
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*/
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const uint32_t nop = gpuver >= 6 ? 0x1000000 : 0x0;
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if (instrs[pc] != nop) {
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printerr("[%08x]", instrs[pc]);
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printf(" ; ");
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}
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if (rep)
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printf("(rep)");
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printf("nop");
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print_gpu_reg(instrs[pc]);
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break;
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}
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case OPC_ADD:
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case OPC_ADDHI:
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case OPC_SUB:
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case OPC_SUBHI:
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case OPC_AND:
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case OPC_OR:
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case OPC_XOR:
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case OPC_NOT:
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case OPC_SHL:
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case OPC_USHR:
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case OPC_ISHR:
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case OPC_ROT:
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case OPC_MUL8:
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case OPC_MIN:
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case OPC_MAX:
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case OPC_CMP: {
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bool src1 = true;
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if (opc == OPC_NOT)
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src1 = false;
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if (rep)
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printf("(rep)");
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print_alu_name(opc, instrs[pc]);
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print_dst(instr->alui.dst);
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printf(", ");
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if (src1) {
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print_src(instr->alui.src);
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printf(", ");
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}
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printf("0x%04x", instr->alui.uimm);
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print_gpu_reg(instr->alui.uimm);
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/* print out unexpected bits: */
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if (verbose) {
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if (instr->alui.src && !src1)
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printerr(" (src=%02x)", instr->alui.src);
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}
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break;
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}
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case OPC_MOVI: {
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if (rep)
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printf("(rep)");
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printf("mov ");
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print_dst(instr->movi.dst);
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printf(", 0x%04x", instr->movi.uimm);
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if (instr->movi.shift)
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printf(" << %u", instr->movi.shift);
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/* using mov w/ << 16 is popular way to construct a pkt7
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* header to send (for ex, from PFP to ME), so check that
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* case first
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*/
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if ((instr->movi.shift == 16) &&
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((instr->movi.uimm & 0xff00) == 0x7000)) {
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unsigned opc, p;
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opc = instr->movi.uimm & 0x7f;
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p = pm4_odd_parity_bit(opc);
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/* So, you'd think that checking the parity bit would be
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* a good way to rule out false positives, but seems like
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* ME doesn't really care.. at least it would filter out
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* things that look like actual legit packets between
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* PFP and ME..
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*/
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if (1 || p == ((instr->movi.uimm >> 7) & 0x1)) {
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const char *name = getpm4(opc);
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printf("\t; ");
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if (name)
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printlbl("%s", name);
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else
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printlbl("UNKN%u", opc);
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break;
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}
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}
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print_gpu_reg(instr->movi.uimm << instr->movi.shift);
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break;
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}
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case OPC_ALU: {
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bool src1 = true;
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if (instr->alu.alu == OPC_NOT || instr->alu.alu == OPC_MSB)
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src1 = false;
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if (instr->alu.pad)
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printf("[%08x] ; ", instrs[pc]);
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if (rep)
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printf("(rep)");
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if (instr->alu.xmov)
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printf("(xmov%d)", instr->alu.xmov);
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/* special case mnemonics:
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* reading $00 seems to always yield zero, and so:
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* or $dst, $00, $src -> mov $dst, $src
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* Maybe add one for negate too, ie.
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* sub $dst, $00, $src ???
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*/
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if ((instr->alu.alu == OPC_OR) && !instr->alu.src1) {
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printf("mov ");
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src1 = false;
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} else {
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print_alu_name(instr->alu.alu, instrs[pc]);
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}
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print_dst(instr->alu.dst);
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if (src1) {
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printf(", ");
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print_src(instr->alu.src1);
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}
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printf(", ");
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print_src(instr->alu.src2);
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/* print out unexpected bits: */
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if (verbose) {
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if (instr->alu.pad)
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printerr(" (pad=%01x)", instr->alu.pad);
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if (instr->alu.src1 && !src1)
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printerr(" (src1=%02x)", instr->alu.src1);
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}
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/* xmov is a modifier that makes the processor execute up to 3
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* extra mov's after the current instruction. Given an ALU
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* instruction:
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*
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* (xmovN) alu $dst, $src1, $src2
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*
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* In all of the uses in the firmware blob, $dst and $src2 are one
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* of the "special" registers $data, $addr, $addr2. I've observed
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* that if $dst isn't "special" then it's replaced with $00
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* instead of $data, but I haven't checked what happens if $src2
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* isn't "special". Anyway, in the usual case, the HW produces a
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* count M = min(N, $rem) and then does the following:
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*
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* M = 1:
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* mov $data, $src2
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*
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* M = 2:
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* mov $data, $src2
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* mov $data, $src2
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*
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* M = 3:
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* mov $data, $src2
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* mov $dst, $src2 (special case for CP_CONTEXT_REG_BUNCH)
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* mov $data, $src2
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*
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* It seems to be frequently used in combination with (rep) to
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* provide a kind of hardware-based loop unrolling, and there's
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* even a special case in the ISA to be able to do this with
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* CP_CONTEXT_REG_BUNCH. However (rep) isn't required.
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*
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* This dumps the expected extra instructions, assuming that $rem
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* isn't too small.
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*/
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if (verbose && instr->alu.xmov) {
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for (int i = 0; i < instr->alu.xmov; i++) {
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printf("\n ; mov ");
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if (instr->alu.dst < 0x1d)
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printf("$00");
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else if (instr->alu.xmov == 3 && i == 1)
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print_dst(instr->alu.dst);
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else
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printf("$data");
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printf(", ");
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print_src(instr->alu.src2);
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}
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}
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break;
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}
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case OPC_CWRITE6:
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case OPC_CREAD6:
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case OPC_STORE6:
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case OPC_LOAD6: {
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if (rep)
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printf("(rep)");
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bool is_control_reg = true;
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if (gpuver >= 6) {
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switch (opc) {
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case OPC_CWRITE6:
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printf("cwrite ");
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break;
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case OPC_CREAD6:
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printf("cread ");
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break;
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case OPC_STORE6:
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is_control_reg = false;
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printf("store ");
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break;
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case OPC_LOAD6:
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is_control_reg = false;
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printf("load ");
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break;
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default:
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assert(!"unreachable");
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}
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} else {
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switch (opc) {
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case OPC_CWRITE5:
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printf("cwrite ");
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break;
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case OPC_CREAD5:
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printf("cread ");
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break;
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default:
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fprintf(stderr, "A6xx control opcode on A5xx?\n");
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exit(1);
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}
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}
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print_src(instr->control.src1);
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printf(", [");
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print_src(instr->control.src2);
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printf(" + ");
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if (is_control_reg && instr->control.flags != 0x4)
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print_control_reg(instr->control.uimm);
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else
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printf("0x%03x", instr->control.uimm);
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printf("], 0x%x", instr->control.flags);
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break;
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}
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case OPC_BRNEI:
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case OPC_BREQI:
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case OPC_BRNEB:
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case OPC_BREQB: {
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unsigned off = pc + instr->br.ioff;
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assert(!rep);
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/* Since $00 reads back zero, it can be used as src for
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* unconditional branches. (This only really makes sense
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* for the BREQB.. or possible BRNEI if imm==0.)
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*
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* If bit=0 then branch is taken if *all* bits are zero.
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* Otherwise it is taken if bit (bit-1) is clear.
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*
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* Note the instruction after a jump/branch is executed
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* regardless of whether branch is taken, so use nop or
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* take that into account in code.
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*/
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if (instr->br.src || (opc != OPC_BRNEB)) {
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bool immed = false;
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if (opc == OPC_BRNEI) {
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printf("brne ");
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immed = true;
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} else if (opc == OPC_BREQI) {
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printf("breq ");
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immed = true;
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} else if (opc == OPC_BRNEB) {
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printf("brne ");
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} else if (opc == OPC_BREQB) {
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printf("breq ");
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}
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print_src(instr->br.src);
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if (immed) {
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printf(", 0x%x,", instr->br.bit_or_imm);
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} else {
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printf(", b%u,", instr->br.bit_or_imm);
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}
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} else {
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printf("jump");
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if (verbose && instr->br.bit_or_imm) {
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printerr(" (src=%03x, bit=%03x) ", instr->br.src,
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instr->br.bit_or_imm);
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}
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}
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printf(" #");
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printlbl("%s", label_name(off, true));
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if (verbose)
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printf(" (#%d, %04x)", instr->br.ioff, off);
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break;
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}
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case OPC_CALL:
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assert(!rep);
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printf("call #");
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printlbl("%s", fxn_name(instr->call.uoff));
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if (verbose) {
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printf(" (%04x)", instr->call.uoff);
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if (instr->br.bit_or_imm || instr->br.src) {
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printerr(" (src=%03x, bit=%03x) ", instr->br.src,
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instr->br.bit_or_imm);
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}
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}
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break;
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case OPC_RET:
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assert(!rep);
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if (instr->ret.pad)
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printf("[%08x] ; ", instrs[pc]);
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if (instr->ret.interrupt)
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printf("iret");
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else
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printf("ret");
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break;
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case OPC_WIN:
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assert(!rep);
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if (instr->waitin.pad)
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printf("[%08x] ; ", instrs[pc]);
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printf("waitin");
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if (verbose && instr->waitin.pad)
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printerr(" (pad=%x)", instr->waitin.pad);
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break;
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case OPC_PREEMPTLEAVE6:
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if (gpuver < 6) {
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printf("[%08x] ; op38", instrs[pc]);
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} else {
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printf("preemptleave #");
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printlbl("%s", label_name(instr->call.uoff, true));
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}
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break;
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case OPC_SETSECURE:
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/* Note: This seems to implicitly read the secure/not-secure state
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* to set from the low bit of $02, and implicitly jumps to pc + 3
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* (i.e. skipping the next two instructions) if it succeeds. We
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* print these implicit parameters to make reading the disassembly
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* easier.
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*/
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if (instr->pad)
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printf("[%08x] ; ", instrs[pc]);
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printf("setsecure $02, #");
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printlbl("%s", label_name(pc + 3, true));
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break;
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default:
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printerr("[%08x]", instrs[pc]);
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printf(" ; op%02x ", opc);
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print_dst(instr->alui.dst);
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printf(", ");
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print_src(instr->alui.src);
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print_gpu_reg(instrs[pc] & 0xffff);
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break;
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}
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printf("\n");
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}
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static void
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disasm(uint32_t *buf, int sizedwords)
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{
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@ -350,407 +756,7 @@ disasm(uint32_t *buf, int sizedwords)
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/* print instructions: */
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for (i = 0; i < jmptbl_start; i++) {
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int jump_label_idx;
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afuc_instr *instr = (void *)&instrs[i];
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const char *fname, *lname;
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afuc_opc opc;
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bool rep;
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afuc_get_opc(instr, &opc, &rep);
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lname = label_name(i, false);
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fname = fxn_name(i);
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jump_label_idx = get_jump_table_entry(i);
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if (jump_label_idx >= 0) {
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int j;
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printf("\n");
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for (j = 0; j < jump_labels[jump_label_idx].num_jump_labels; j++) {
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uint32_t jump_label = jump_labels[jump_label_idx].jump_labels[j];
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const char *name = getpm4(jump_label);
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if (name) {
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printlbl("%s", name);
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} else {
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printlbl("UNKN%d", jump_label);
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}
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printf(":\n");
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}
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}
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if (fname) {
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printlbl("%s", fname);
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printf(":\n");
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}
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if (lname) {
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printlbl(" %s", lname);
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printf(":");
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} else {
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printf(" ");
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}
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if (verbose) {
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printf("\t%04x: %08x ", i, instrs[i]);
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} else {
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printf(" ");
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}
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switch (opc) {
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case OPC_NOP: {
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/* a6xx changed the default immediate, and apparently 0
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* is illegal now.
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*/
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const uint32_t nop = gpuver >= 6 ? 0x1000000 : 0x0;
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if (instrs[i] != nop) {
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printerr("[%08x]", instrs[i]);
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printf(" ; ");
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}
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if (rep)
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printf("(rep)");
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printf("nop");
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print_gpu_reg(instrs[i]);
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break;
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}
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case OPC_ADD:
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case OPC_ADDHI:
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case OPC_SUB:
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case OPC_SUBHI:
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case OPC_AND:
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case OPC_OR:
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case OPC_XOR:
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case OPC_NOT:
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case OPC_SHL:
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case OPC_USHR:
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case OPC_ISHR:
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case OPC_ROT:
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case OPC_MUL8:
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case OPC_MIN:
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case OPC_MAX:
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case OPC_CMP: {
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bool src1 = true;
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||||
if (opc == OPC_NOT)
|
||||
src1 = false;
|
||||
|
||||
if (rep)
|
||||
printf("(rep)");
|
||||
|
||||
print_alu_name(opc, instrs[i]);
|
||||
print_dst(instr->alui.dst);
|
||||
printf(", ");
|
||||
if (src1) {
|
||||
print_src(instr->alui.src);
|
||||
printf(", ");
|
||||
}
|
||||
printf("0x%04x", instr->alui.uimm);
|
||||
print_gpu_reg(instr->alui.uimm);
|
||||
|
||||
/* print out unexpected bits: */
|
||||
if (verbose) {
|
||||
if (instr->alui.src && !src1)
|
||||
printerr(" (src=%02x)", instr->alui.src);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case OPC_MOVI: {
|
||||
if (rep)
|
||||
printf("(rep)");
|
||||
printf("mov ");
|
||||
print_dst(instr->movi.dst);
|
||||
printf(", 0x%04x", instr->movi.uimm);
|
||||
if (instr->movi.shift)
|
||||
printf(" << %u", instr->movi.shift);
|
||||
|
||||
/* using mov w/ << 16 is popular way to construct a pkt7
|
||||
* header to send (for ex, from PFP to ME), so check that
|
||||
* case first
|
||||
*/
|
||||
if ((instr->movi.shift == 16) &&
|
||||
((instr->movi.uimm & 0xff00) == 0x7000)) {
|
||||
unsigned opc, p;
|
||||
|
||||
opc = instr->movi.uimm & 0x7f;
|
||||
p = pm4_odd_parity_bit(opc);
|
||||
|
||||
/* So, you'd think that checking the parity bit would be
|
||||
* a good way to rule out false positives, but seems like
|
||||
* ME doesn't really care.. at least it would filter out
|
||||
* things that look like actual legit packets between
|
||||
* PFP and ME..
|
||||
*/
|
||||
if (1 || p == ((instr->movi.uimm >> 7) & 0x1)) {
|
||||
const char *name = getpm4(opc);
|
||||
printf("\t; ");
|
||||
if (name)
|
||||
printlbl("%s", name);
|
||||
else
|
||||
printlbl("UNKN%u", opc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
print_gpu_reg(instr->movi.uimm << instr->movi.shift);
|
||||
|
||||
break;
|
||||
}
|
||||
case OPC_ALU: {
|
||||
bool src1 = true;
|
||||
|
||||
if (instr->alu.alu == OPC_NOT || instr->alu.alu == OPC_MSB)
|
||||
src1 = false;
|
||||
|
||||
if (instr->alu.pad)
|
||||
printf("[%08x] ; ", instrs[i]);
|
||||
|
||||
if (rep)
|
||||
printf("(rep)");
|
||||
if (instr->alu.xmov)
|
||||
printf("(xmov%d)", instr->alu.xmov);
|
||||
|
||||
/* special case mnemonics:
|
||||
* reading $00 seems to always yield zero, and so:
|
||||
* or $dst, $00, $src -> mov $dst, $src
|
||||
* Maybe add one for negate too, ie.
|
||||
* sub $dst, $00, $src ???
|
||||
*/
|
||||
if ((instr->alu.alu == OPC_OR) && !instr->alu.src1) {
|
||||
printf("mov ");
|
||||
src1 = false;
|
||||
} else {
|
||||
print_alu_name(instr->alu.alu, instrs[i]);
|
||||
}
|
||||
|
||||
print_dst(instr->alu.dst);
|
||||
if (src1) {
|
||||
printf(", ");
|
||||
print_src(instr->alu.src1);
|
||||
}
|
||||
printf(", ");
|
||||
print_src(instr->alu.src2);
|
||||
|
||||
/* print out unexpected bits: */
|
||||
if (verbose) {
|
||||
if (instr->alu.pad)
|
||||
printerr(" (pad=%01x)", instr->alu.pad);
|
||||
if (instr->alu.src1 && !src1)
|
||||
printerr(" (src1=%02x)", instr->alu.src1);
|
||||
}
|
||||
|
||||
/* xmov is a modifier that makes the processor execute up to 3
|
||||
* extra mov's after the current instruction. Given an ALU
|
||||
* instruction:
|
||||
*
|
||||
* (xmovN) alu $dst, $src1, $src2
|
||||
*
|
||||
* In all of the uses in the firmware blob, $dst and $src2 are one
|
||||
* of the "special" registers $data, $addr, $addr2. I've observed
|
||||
* that if $dst isn't "special" then it's replaced with $00
|
||||
* instead of $data, but I haven't checked what happens if $src2
|
||||
* isn't "special". Anyway, in the usual case, the HW produces a
|
||||
* count M = min(N, $rem) and then does the following:
|
||||
*
|
||||
* M = 1:
|
||||
* mov $data, $src2
|
||||
*
|
||||
* M = 2:
|
||||
* mov $data, $src2
|
||||
* mov $data, $src2
|
||||
*
|
||||
* M = 3:
|
||||
* mov $data, $src2
|
||||
* mov $dst, $src2 (special case for CP_CONTEXT_REG_BUNCH)
|
||||
* mov $data, $src2
|
||||
*
|
||||
* It seems to be frequently used in combination with (rep) to
|
||||
* provide a kind of hardware-based loop unrolling, and there's
|
||||
* even a special case in the ISA to be able to do this with
|
||||
* CP_CONTEXT_REG_BUNCH. However (rep) isn't required.
|
||||
*
|
||||
* This dumps the expected extra instructions, assuming that $rem
|
||||
* isn't too small.
|
||||
*/
|
||||
if (verbose && instr->alu.xmov) {
|
||||
for (int i = 0; i < instr->alu.xmov; i++) {
|
||||
printf("\n ; mov ");
|
||||
if (instr->alu.dst < 0x1d)
|
||||
printf("$00");
|
||||
else if (instr->alu.xmov == 3 && i == 1)
|
||||
print_dst(instr->alu.dst);
|
||||
else
|
||||
printf("$data");
|
||||
printf(", ");
|
||||
print_src(instr->alu.src2);
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case OPC_CWRITE6:
|
||||
case OPC_CREAD6:
|
||||
case OPC_STORE6:
|
||||
case OPC_LOAD6: {
|
||||
if (rep)
|
||||
printf("(rep)");
|
||||
|
||||
bool is_control_reg = true;
|
||||
if (gpuver >= 6) {
|
||||
switch (opc) {
|
||||
case OPC_CWRITE6:
|
||||
printf("cwrite ");
|
||||
break;
|
||||
case OPC_CREAD6:
|
||||
printf("cread ");
|
||||
break;
|
||||
case OPC_STORE6:
|
||||
is_control_reg = false;
|
||||
printf("store ");
|
||||
break;
|
||||
case OPC_LOAD6:
|
||||
is_control_reg = false;
|
||||
printf("load ");
|
||||
break;
|
||||
default:
|
||||
assert(!"unreachable");
|
||||
}
|
||||
} else {
|
||||
switch (opc) {
|
||||
case OPC_CWRITE5:
|
||||
printf("cwrite ");
|
||||
break;
|
||||
case OPC_CREAD5:
|
||||
printf("cread ");
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "A6xx control opcode on A5xx?\n");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
print_src(instr->control.src1);
|
||||
printf(", [");
|
||||
print_src(instr->control.src2);
|
||||
printf(" + ");
|
||||
if (is_control_reg && instr->control.flags != 0x4)
|
||||
print_control_reg(instr->control.uimm);
|
||||
else
|
||||
printf("0x%03x", instr->control.uimm);
|
||||
printf("], 0x%x", instr->control.flags);
|
||||
break;
|
||||
}
|
||||
case OPC_BRNEI:
|
||||
case OPC_BREQI:
|
||||
case OPC_BRNEB:
|
||||
case OPC_BREQB: {
|
||||
unsigned off = i + instr->br.ioff;
|
||||
|
||||
assert(!rep);
|
||||
|
||||
/* Since $00 reads back zero, it can be used as src for
|
||||
* unconditional branches. (This only really makes sense
|
||||
* for the BREQB.. or possible BRNEI if imm==0.)
|
||||
*
|
||||
* If bit=0 then branch is taken if *all* bits are zero.
|
||||
* Otherwise it is taken if bit (bit-1) is clear.
|
||||
*
|
||||
* Note the instruction after a jump/branch is executed
|
||||
* regardless of whether branch is taken, so use nop or
|
||||
* take that into account in code.
|
||||
*/
|
||||
if (instr->br.src || (opc != OPC_BRNEB)) {
|
||||
bool immed = false;
|
||||
|
||||
if (opc == OPC_BRNEI) {
|
||||
printf("brne ");
|
||||
immed = true;
|
||||
} else if (opc == OPC_BREQI) {
|
||||
printf("breq ");
|
||||
immed = true;
|
||||
} else if (opc == OPC_BRNEB) {
|
||||
printf("brne ");
|
||||
} else if (opc == OPC_BREQB) {
|
||||
printf("breq ");
|
||||
}
|
||||
print_src(instr->br.src);
|
||||
if (immed) {
|
||||
printf(", 0x%x,", instr->br.bit_or_imm);
|
||||
} else {
|
||||
printf(", b%u,", instr->br.bit_or_imm);
|
||||
}
|
||||
} else {
|
||||
printf("jump");
|
||||
if (verbose && instr->br.bit_or_imm) {
|
||||
printerr(" (src=%03x, bit=%03x) ", instr->br.src,
|
||||
instr->br.bit_or_imm);
|
||||
}
|
||||
}
|
||||
|
||||
printf(" #");
|
||||
printlbl("%s", label_name(off, true));
|
||||
if (verbose)
|
||||
printf(" (#%d, %04x)", instr->br.ioff, off);
|
||||
break;
|
||||
}
|
||||
case OPC_CALL:
|
||||
assert(!rep);
|
||||
printf("call #");
|
||||
printlbl("%s", fxn_name(instr->call.uoff));
|
||||
if (verbose) {
|
||||
printf(" (%04x)", instr->call.uoff);
|
||||
if (instr->br.bit_or_imm || instr->br.src) {
|
||||
printerr(" (src=%03x, bit=%03x) ", instr->br.src,
|
||||
instr->br.bit_or_imm);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case OPC_RET:
|
||||
assert(!rep);
|
||||
if (instr->ret.pad)
|
||||
printf("[%08x] ; ", instrs[i]);
|
||||
if (instr->ret.interrupt)
|
||||
printf("iret");
|
||||
else
|
||||
printf("ret");
|
||||
break;
|
||||
case OPC_WIN:
|
||||
assert(!rep);
|
||||
if (instr->waitin.pad)
|
||||
printf("[%08x] ; ", instrs[i]);
|
||||
printf("waitin");
|
||||
if (verbose && instr->waitin.pad)
|
||||
printerr(" (pad=%x)", instr->waitin.pad);
|
||||
break;
|
||||
case OPC_PREEMPTLEAVE6:
|
||||
if (gpuver < 6) {
|
||||
printf("[%08x] ; op38", instrs[i]);
|
||||
} else {
|
||||
printf("preemptleave #");
|
||||
printlbl("%s", label_name(instr->call.uoff, true));
|
||||
}
|
||||
break;
|
||||
case OPC_SETSECURE:
|
||||
/* Note: This seems to implicitly read the secure/not-secure state
|
||||
* to set from the low bit of $02, and implicitly jumps to pc + 3
|
||||
* (i.e. skipping the next two instructions) if it succeeds. We
|
||||
* print these implicit parameters to make reading the disassembly
|
||||
* easier.
|
||||
*/
|
||||
if (instr->pad)
|
||||
printf("[%08x] ; ", instrs[i]);
|
||||
printf("setsecure $02, #");
|
||||
printlbl("%s", label_name(i + 3, true));
|
||||
break;
|
||||
default:
|
||||
printerr("[%08x]", instrs[i]);
|
||||
printf(" ; op%02x ", opc);
|
||||
print_dst(instr->alui.dst);
|
||||
printf(", ");
|
||||
print_src(instr->alui.src);
|
||||
print_gpu_reg(instrs[i] & 0xffff);
|
||||
break;
|
||||
}
|
||||
printf("\n");
|
||||
disasm_instr(instrs, i);
|
||||
}
|
||||
|
||||
/* print jumptable: */
|
||||
|
|
|
|||
Loading…
Reference in New Issue